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uasal / firmware Public

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Testbench initialization#7

Open

eselznick2 wants to merge 25 commits intomasteruasal/firmware:masterfrom

testbench-initializationuasal/firmware:testbench-initializationCopy head branch name to clipboard

Conversation Commits25 (25)Checks Files changed

Open

Testbench initialization#7
eselznick2 wants to merge 25 commits intomasterfrom
testbench-initialization

Commits

Commits on Apr 12, 2026

initial testbench Makefile / ClockDivider_tb
eselznick2
committed
refactor build flow, test check action
eselznick2
committed
This is an intentional fail, checking email system
eselznick2
committed
reverting intentional failure
eselznick2
committed
renamed workflow to build-and-test
eselznick2
committed
oneshots, counters, and dividers
eselznick2
committed
fifo, peek, revamp make all
eselznick2
committed
changes to files
eselznick2
committed
fixed intialization all tb and files, crc bytes, rm pop from fifo_peek
eselznick2
committed
crc stream and crc fifo
eselznick2
committed
added UartTx and UartTxParity tb, UartTxParityBusy fix
eselznick2
committed
Makefile simplification, its still ugly though
eselznick2
committed
UartRxRaw tb
eselznick2
committed
UartRx and UartRx Parity fixes (Err Flag)
eselznick2
committed
VariableClockDivider and VariableClockDivider2X
eselznick2
committed
UartFifos work in progress, investigating fifo changes
eselznick2
committed
disabling UartRxFifoExtClk and UartRxFifoExtClkPeek tb, work in progress
eselznick2
committed

Commits on Apr 13, 2026

FieldLatcher, new PeekRingBuffer, PatternFinder
eselznick2
committed
small changes
eselznick2
committed
allow PeekRingBuffer to pass despite PayLoadLen questionable
eselznick2
committed

Commits on Apr 16, 2026

standardized ClockDividers, OneShots
eselznick2
committed
make crc init value a generic (FFFFFFFF or XXXXXXXX)
eselznick2
committed

Commits on Apr 21, 2026

Uart TX/RX fifo tbs, gated fifo/peek tbs
eselznick2
committed
add UartRX/TX and Gated tbs (new files)
eselznick2
committed
quality
eselznick2
committed

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