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3 changes: 0 additions & 3 deletions generators/chipyard/src/main/scala/example/TutorialTile.scala
Original file line number Diff line number Diff line change
Expand Up @@ -171,9 +171,6 @@ class MyTile(

// DOC include start: Implementation class
class MyTileModuleImp(outer: MyTile) extends BaseTileModuleImp(outer){
// annotate the parameters
Annotated.params(this, outer.myParams)

// TODO: Create the top module of the core and connect it with the ports in "outer"

// If your core is in Verilog (assume your blackbox is called "MyCoreBlackbox"), instantiate it here like
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2 changes: 1 addition & 1 deletion generators/cva6
2 changes: 1 addition & 1 deletion generators/ibex
2 changes: 1 addition & 1 deletion generators/radiance
2 changes: 1 addition & 1 deletion generators/riscv-sodor
2 changes: 1 addition & 1 deletion generators/shuttle
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