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@tymcauley tymcauley commented Mar 7, 2025

See chipsalliance/rocket-chip#3723

Related PRs / Issues:
#2205

Type of change:

  • Bug fix
  • New feature
  • Other enhancement

Impact:

  • RTL change
  • Software change (RISC-V software)
  • Build system change
  • Other

Contributor Checklist:

  • Did you set main as the base branch?
  • Is this PR's title suitable for inclusion in the changelog and have you added a changelog:<topic> label?
  • Did you state the type-of-change/impact?
  • Did you delete any extraneous prints/debugging code?
  • Did you mark the PR with a changelog: label?
  • (If applicable) Did you update the conda .conda-lock.yml file if you updated the conda requirements file?
  • (If applicable) Did you add documentation for the feature?
  • (If applicable) Did you add a test demonstrating the PR?
  • (If applicable) Did you mark the PR as Please Backport?

CI Help:
Add the following labels to modify the CI for a set of features.
Generally, a label added only affect subsequent changes to the PR (i.e. new commits, force pushing, closing/reopening).
See ci:* for full list of labels:

  • ci:fpga-deploy - Run FPGA-based E2E testing
  • ci:local-fpga-buildbitstream-deploy - Build local FPGA bitstreams for platforms that are released
  • ci:disable - Disable CI

@tymcauley tymcauley force-pushed the remove-chisel-annos branch from 62daa07 to 85588cb Compare March 7, 2025 19:35
@tymcauley
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All of the submodule bumps have been merged, so this is ready from my side.

@jerryz123
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Yep, this looks like it should pass CI

@jerryz123 jerryz123 merged commit 4edb82f into ucb-bar:main Mar 7, 2025
68 of 70 checks passed
@tymcauley tymcauley deleted the remove-chisel-annos branch March 7, 2025 23:36
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2 participants