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[Draft][wip]Mimic vector composition hierarchy for accumulators. #433

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[Draft][wip]Mimic vector composition hierarchy for accumulators. #433

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a29f3d4
[wip] revert separate subregister index for accumulator
niwinanto Apr 9, 2025
94e6788
[wip] Create dummy 256-bit accumulator and compose it with 512-bit to…
niwinanto Apr 9, 2025
ac87c2e
[WIP] Spill to register instead of stack
niwinanto Mar 27, 2025
0575190
[wip]Extend vector composite register class with fifo registers
niwinanto Apr 10, 2025
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91 changes: 59 additions & 32 deletions llvm/lib/Target/AIE/aie2p/AIE2PInstrInfo.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -618,22 +618,22 @@ void AIE2PInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
} else if (AIE2P::VEC1024RegClass.contains(SrcReg) &&
AIE2P::ACC1024RegClass.contains(DstReg)) {
BuildMI(MBB, MBBI, DL, get(AIE2P::VMOV_alu_mv_mv_x),
TRI.getSubReg(DstReg, AIE2P::sub_512_acc_lo))
TRI.getSubReg(DstReg, AIE2P::sub_512_lo))
.addReg(TRI.getSubReg(SrcReg, AIE2P::sub_512_lo),
getKillRegState(KillSrc));
BuildMI(MBB, MBBI, DL, get(AIE2P::VMOV_alu_mv_mv_x),
TRI.getSubReg(DstReg, AIE2P::sub_512_acc_hi))
TRI.getSubReg(DstReg, AIE2P::sub_512_hi))
.addReg(TRI.getSubReg(SrcReg, AIE2P::sub_512_hi),
getKillRegState(KillSrc));
} else if (AIE2P::ACC1024RegClass.contains(SrcReg) &&
AIE2P::VEC1024RegClass.contains(DstReg)) {
BuildMI(MBB, MBBI, DL, get(AIE2P::VMOV_alu_mv_mv_x),
TRI.getSubReg(DstReg, AIE2P::sub_512_lo))
.addReg(TRI.getSubReg(SrcReg, AIE2P::sub_512_acc_lo),
.addReg(TRI.getSubReg(SrcReg, AIE2P::sub_512_lo),
getKillRegState(KillSrc));
BuildMI(MBB, MBBI, DL, get(AIE2P::VMOV_alu_mv_mv_x),
TRI.getSubReg(DstReg, AIE2P::sub_512_hi))
.addReg(TRI.getSubReg(SrcReg, AIE2P::sub_512_acc_hi),
.addReg(TRI.getSubReg(SrcReg, AIE2P::sub_512_hi),
getKillRegState(KillSrc));
} else if ((AIE2P::ACC2048RegClass.contains(SrcReg)) &&
(AIE2P::ACC2048RegClass.contains(DstReg))) {
Expand Down Expand Up @@ -684,52 +684,52 @@ void AIE2PInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
} else if ((AIE2P::FIFO1024RegClass.contains(SrcReg)) &&
(AIE2P::FIFO1024RegClass.contains(DstReg))) {
BuildMI(MBB, MBBI, DL, get(AIE2P::VMOV_alu_mv_mv_x),
TRI.getSubReg(DstReg, AIE2P::sub_lo_fifo))
.addReg(TRI.getSubReg(SrcReg, AIE2P::sub_lo_fifo),
TRI.getSubReg(DstReg, AIE2P::sub_512_lo))
.addReg(TRI.getSubReg(SrcReg, AIE2P::sub_512_lo),
getKillRegState(KillSrc));
BuildMI(MBB, MBBI, DL, get(AIE2P::VMOV_alu_mv_mv_x),
TRI.getSubReg(DstReg, AIE2P::sub_hi_fifo))
.addReg(TRI.getSubReg(SrcReg, AIE2P::sub_hi_fifo),
TRI.getSubReg(DstReg, AIE2P::sub_512_hi))
.addReg(TRI.getSubReg(SrcReg, AIE2P::sub_512_hi),
getKillRegState(KillSrc));
} else if ((AIE2P::VEC1024RegClass.contains(SrcReg)) &&
(AIE2P::FIFO1024RegClass.contains(DstReg))) {
BuildMI(MBB, MBBI, DL, get(AIE2P::VMOV_alu_mv_mv_x),
TRI.getSubReg(DstReg, AIE2P::sub_lo_fifo))
TRI.getSubReg(DstReg, AIE2P::sub_512_lo))
.addReg(TRI.getSubReg(SrcReg, AIE2P::sub_512_lo),
getKillRegState(KillSrc));
BuildMI(MBB, MBBI, DL, get(AIE2P::VMOV_alu_mv_mv_x),
TRI.getSubReg(DstReg, AIE2P::sub_hi_fifo))
TRI.getSubReg(DstReg, AIE2P::sub_512_hi))
.addReg(TRI.getSubReg(SrcReg, AIE2P::sub_512_hi),
getKillRegState(KillSrc));
} else if ((AIE2P::FIFO1024RegClass.contains(SrcReg)) &&
(AIE2P::VEC1024RegClass.contains(DstReg))) {
BuildMI(MBB, MBBI, DL, get(AIE2P::VMOV_alu_mv_mv_x),
TRI.getSubReg(DstReg, AIE2P::sub_512_lo))
.addReg(TRI.getSubReg(SrcReg, AIE2P::sub_lo_fifo),
.addReg(TRI.getSubReg(SrcReg, AIE2P::sub_512_lo),
getKillRegState(KillSrc));
BuildMI(MBB, MBBI, DL, get(AIE2P::VMOV_alu_mv_mv_x),
TRI.getSubReg(DstReg, AIE2P::sub_512_hi))
.addReg(TRI.getSubReg(SrcReg, AIE2P::sub_hi_fifo),
.addReg(TRI.getSubReg(SrcReg, AIE2P::sub_512_hi),
getKillRegState(KillSrc));
} else if ((AIE2P::ACC1024RegClass.contains(SrcReg)) &&
(AIE2P::FIFO1024RegClass.contains(DstReg))) {
BuildMI(MBB, MBBI, DL, get(AIE2P::VMOV_alu_mv_mv_x),
TRI.getSubReg(DstReg, AIE2P::sub_lo_fifo))
.addReg(TRI.getSubReg(SrcReg, AIE2P::sub_512_acc_lo),
TRI.getSubReg(DstReg, AIE2P::sub_512_lo))
.addReg(TRI.getSubReg(SrcReg, AIE2P::sub_512_lo),
getKillRegState(KillSrc));
BuildMI(MBB, MBBI, DL, get(AIE2P::VMOV_alu_mv_mv_x),
TRI.getSubReg(DstReg, AIE2P::sub_hi_fifo))
.addReg(TRI.getSubReg(SrcReg, AIE2P::sub_512_acc_hi),
TRI.getSubReg(DstReg, AIE2P::sub_512_hi))
.addReg(TRI.getSubReg(SrcReg, AIE2P::sub_512_hi),
getKillRegState(KillSrc));
} else if ((AIE2P::FIFO1024RegClass.contains(SrcReg)) &&
(AIE2P::ACC1024RegClass.contains(DstReg))) {
BuildMI(MBB, MBBI, DL, get(AIE2P::VMOV_alu_mv_mv_x),
TRI.getSubReg(DstReg, AIE2P::sub_512_acc_lo))
.addReg(TRI.getSubReg(SrcReg, AIE2P::sub_lo_fifo),
TRI.getSubReg(DstReg, AIE2P::sub_512_lo))
.addReg(TRI.getSubReg(SrcReg, AIE2P::sub_512_lo),
getKillRegState(KillSrc));
BuildMI(MBB, MBBI, DL, get(AIE2P::VMOV_alu_mv_mv_x),
TRI.getSubReg(DstReg, AIE2P::sub_512_acc_hi))
.addReg(TRI.getSubReg(SrcReg, AIE2P::sub_hi_fifo),
TRI.getSubReg(DstReg, AIE2P::sub_512_hi))
.addReg(TRI.getSubReg(SrcReg, AIE2P::sub_512_hi),
getKillRegState(KillSrc));
} else if ((AIE2P::eLRegClass.contains(SrcReg)) &&
(AIE2P::EXPVEC64RegClass.contains(DstReg))) {
Expand All @@ -755,6 +755,7 @@ void AIE2PInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
(AIE2P::ePSRFLdFRegClass.contains(DstReg))) {
copyThroughSubRegs(MBB, MBBI, DL, DstReg, SrcReg, KillSrc);
} else {
LLVM_DEBUG(MBBI->dump(););
llvm_unreachable("unhandled case in copyPhysReg");
}
}
Expand Down Expand Up @@ -913,6 +914,18 @@ void AIE2PInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
Opcode = AIE2P::VST_E_SPILL;
} else if (regClassMatches(AIE2P::VEC576RegClass, RC, SrcReg)) {
Opcode = AIE2P::VST_EX_SPILL;
} else if (regClassMatches(AIE2P::spill_acc1024_to_compositeRegClass, RC,
SrcReg)) {
Opcode = AIE2P::VST_CM_SPILL;
} else if (regClassMatches(AIE2P::spill_acc512_to_compositeRegClass, RC,
SrcReg)) {
Opcode = AIE2P::VST_dmx_sts_bm_spill;
} else if (regClassMatches(AIE2P::spill_vec1024_to_compositeRegClass, RC,
SrcReg)) {
Opcode = AIE2P::VST_Y_SPILL;
} else if (regClassMatches(AIE2P::spill_vec512_to_compositeRegClass, RC,
SrcReg)) {
Opcode = AIE2P::VST_dmx_sts_x_spill;
} else if (regClassMatches(AIE2P::eSRegClass, RC, SrcReg) ||
regClassMatches(AIE2P::spill_eS_to_eRRegClass, RC, SrcReg)) {
// Can't spill these directly. Need to bounce through a GPR.
Expand Down Expand Up @@ -982,6 +995,7 @@ void AIE2PInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
} else if (regClassMatches(AIE2P::ACC2048RegClass, RC, DstReg)) {
Opcode = AIE2P::VLDA_DM_SPILL;
} else if (regClassMatches(AIE2P::ACC1024RegClass, RC, DstReg)) {
I->dump();
Opcode = AIE2P::VLDA_CM_SPILL;
} else if (regClassMatches(AIE2P::FIFO1024RegClass, RC, DstReg)) {
Opcode = AIE2P::VLDA_FIFO_SPILL;
Expand All @@ -999,6 +1013,18 @@ void AIE2PInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
Opcode = AIE2P::VLDA_E_SPILL;
} else if (regClassMatches(AIE2P::VEC576RegClass, RC, DstReg)) {
Opcode = AIE2P::VLDA_EX_SPILL;
} else if (regClassMatches(AIE2P::spill_acc1024_to_compositeRegClass, RC,
DstReg)) {
Opcode = AIE2P::VLDA_CM_SPILL;
} else if (regClassMatches(AIE2P::spill_acc512_to_compositeRegClass, RC,
DstReg)) {
Opcode = AIE2P::VLDA_dmx_lda_bm_spill;
} else if (regClassMatches(AIE2P::spill_vec1024_to_compositeRegClass, RC,
DstReg)) {
Opcode = AIE2P::VLDA_Y_SPILL;
} else if (regClassMatches(AIE2P::spill_vec512_to_compositeRegClass, RC,
DstReg)) {
Opcode = AIE2P::VLDA_dmx_lda_x_spill;
} else if (regClassMatches(AIE2P::eSRegClass, RC, DstReg) ||
regClassMatches(AIE2P::spill_eS_to_eRRegClass, RC, DstReg)) {
// Can't spill these directly. Need to bounce through a GPR.
Expand All @@ -1011,6 +1037,7 @@ void AIE2PInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
.addReg(Reg, getKillRegState(true));
return;
} else {
I->dump();
llvm_unreachable(
"Can't load this register from stack slot: is it virtual?");
}
Expand All @@ -1037,19 +1064,19 @@ AIE2PInstrInfo::getSpillPseudoExpandInfo(const MachineInstr &MI) const {
return {{AIE2P::ST_dms_sts_spill, AIE2P::sub_l_even},
{AIE2P::ST_dms_sts_spill, AIE2P::sub_l_odd}};
case AIE2P::VST_CM_SPILL:
return {{AIE2P::VST_dmx_sts_bm_spill, AIE2P::sub_512_acc_lo},
{AIE2P::VST_dmx_sts_bm_spill, AIE2P::sub_512_acc_hi}};
return {{AIE2P::VST_dmx_sts_bm_spill, AIE2P::sub_512_lo},
{AIE2P::VST_dmx_sts_bm_spill, AIE2P::sub_512_hi}};
case AIE2P::VST_FIFO_SPILL:
return {{AIE2P::VST_dmx_sts_fifohl_spill, AIE2P::sub_lo_fifo},
{AIE2P::VST_dmx_sts_fifohl_spill, AIE2P::sub_hi_fifo}};
return {{AIE2P::VST_dmx_sts_fifohl_spill, AIE2P::sub_512_lo},
{AIE2P::VST_dmx_sts_fifohl_spill, AIE2P::sub_512_hi}};
case AIE2P::VST_PLFR_SPILL:
return {{AIE2P::VST_FIFO_SPILL, AIE2P::sub_fifo},
{AIE2P::ST_dms_sts_spill, AIE2P::sub_avail},
{AIE2P::ST_dms_sts_spill, AIE2P::sub_ptr}};

case AIE2P::VST_DM_SPILL:
return {{AIE2P::VST_CM_SPILL, AIE2P::sub_1024_acc_lo},
{AIE2P::VST_CM_SPILL, AIE2P::sub_1024_acc_hi}};
return {{AIE2P::VST_CM_SPILL, AIE2P::sub_1024_lo},
{AIE2P::VST_CM_SPILL, AIE2P::sub_1024_hi}};
case AIE2P::VST_Y_SPILL:
return {{AIE2P::VST_dmx_sts_x_spill, AIE2P::sub_512_lo},
{AIE2P::VST_dmx_sts_x_spill, AIE2P::sub_512_hi}};
Expand All @@ -1074,20 +1101,20 @@ AIE2PInstrInfo::getSpillPseudoExpandInfo(const MachineInstr &MI) const {
return {{AIE2P::LDA_dms_lda_spill, AIE2P::sub_l_even},
{AIE2P::LDA_dms_lda_spill, AIE2P::sub_l_odd}};
case AIE2P::VLDA_CM_SPILL:
return {{AIE2P::VLDA_dmx_lda_bm_spill, AIE2P::sub_512_acc_lo},
{AIE2P::VLDA_dmx_lda_bm_spill, AIE2P::sub_512_acc_hi}};
return {{AIE2P::VLDA_dmx_lda_bm_spill, AIE2P::sub_512_lo},
{AIE2P::VLDA_dmx_lda_bm_spill, AIE2P::sub_512_hi}};
case AIE2P::VLDA_FIFO_SPILL:
return {{AIE2P::VLDA_dmx_lda_fifohl_spill, AIE2P::sub_lo_fifo},
{AIE2P::VLDA_dmx_lda_fifohl_spill, AIE2P::sub_hi_fifo}};
return {{AIE2P::VLDA_dmx_lda_fifohl_spill, AIE2P::sub_512_lo},
{AIE2P::VLDA_dmx_lda_fifohl_spill, AIE2P::sub_512_hi}};
case AIE2P::VLDA_PLFR_SPILL:
return {
{AIE2P::VLDA_FIFO_SPILL, AIE2P::sub_fifo},
{AIE2P::LDA_dms_lda_spill, AIE2P::sub_avail},
{AIE2P::LDA_dms_lda_spill, AIE2P::sub_ptr},
};
case AIE2P::VLDA_DM_SPILL:
return {{AIE2P::VLDA_CM_SPILL, AIE2P::sub_1024_acc_lo},
{AIE2P::VLDA_CM_SPILL, AIE2P::sub_1024_acc_hi}};
return {{AIE2P::VLDA_CM_SPILL, AIE2P::sub_1024_lo},
{AIE2P::VLDA_CM_SPILL, AIE2P::sub_1024_hi}};
case AIE2P::VLDA_Y_SPILL:
return {{AIE2P::VLDA_dmx_lda_x_spill, AIE2P::sub_512_lo},
{AIE2P::VLDA_dmx_lda_x_spill, AIE2P::sub_512_hi}};
Expand Down
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