Project 31: 10GbE UDP with UART Debug Interface

Part of FPGA Trading Systems Portfolio

This project is part of a complete end-to-end trading system:

• Main Repository: fpga-trading-systems
• Project Number: 31 of 35
• Category: FPGA Core
• Dependencies: None - project will not be updated beyond this point

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Overview

This project integrates the ALINX 10GbE UDP vendor design with a UART debug interface for monitoring network traffic and system status. It serves as the foundation for ITCH market data reception on the AX7325B (Kintex-7 XC7K325T) FPGA.

Key Features

• 10GbE SFP+ Ethernet: Xilinx 10G Ethernet Subsystem with GTX transceivers
• UDP Protocol Stack: Full UDP/IP implementation with ARP handling
• Loopback/Speed Test Modes: Button-controlled mode switching for testing
• UART Debug Output: 115200 baud serial output for monitoring packet counts and status
• LED Status Indicators: Visual feedback for link status and system state

Architecture

+-------------------+     +-------------------+     +-------------------+
|    SFP+ PHY       | --> |   10G Ethernet    | --> |   UDP/IP Stack    |
|   (GTX 10.3125G)  |     |   MAC Subsystem   |     |   (alinx_udp_ip)  |
+-------------------+     +-------------------+     +-------------------+
                                                            |
                          +-------------------+             v
                          |   UART Debug TX   | <-- +-------------------+
                          |   (115200 baud)   |     | UDP Read/Write    |
                          +-------------------+     | Controller        |
                                                    | (Loopback/Speed)  |
                                                    +-------------------+

Hardware Configuration

Network Settings (Configurable in top module)

Parameter	Value
Local IP	192.168.0.215
Local MAC	00:0a:35:01:fe:c0
Destination IP	192.168.0.144
UDP Port	8080

LED Indicators

LED	Status
LED0	PCS Block Locked
LED1	RX Synchronized
LED2	PLL Locked
LED3	UDP Active

Button Functions

Button	Function
BTN0 (rst_n)	System Reset (active low)
BTN1 (push_button)	Toggle Loopback/Speed Mode
BTN2 (debug_btn)	Trigger UART Debug Output

UART Debug Output

Press the debug button to output current status:

10G:Y RX:00000042 TX:00000042

• 10G:Y/N - UDP active status (Y = active, N = inactive)
• RX:xxxxxxxx - Received packet count (hex)
• TX:xxxxxxxx - Transmitted packet count (hex)

Building

Prerequisites

• Vivado 2019.1+ with Enterprise license (required for XC7K325T)
• ALINX UDP IP core (included in ip_repo/) - License required to compile IP

Build Steps

1. Open Vivado and create a new project targeting xc7k325tffg900-2

2. Add source files:

   src/top/udp_10gbe_uart_top.v     (Top-level, set as top)
   src/10gbe/*.v                     (10GbE vendor modules)
   src/uart/uart_tx.vhd             (UART transmitter)
   src/btn/*.vhd                     (Button debouncer, edge detector)
   src/fifo/fifo.vhd                (Generic FIFO)
   

3. Add IP repository path: ip_repo/

4. Add/regenerate Xilinx IP cores:

   • clk_wiz_0: 200 MHz input, 100 MHz + 200 MHz outputs
   • axi_10g_ethernet: 10GBASE-R with shared logic in core
   • axis_fifo: 74-bit x 512 deep
   • udp_ip_0: Custom UDP/IP stack from ip_repo

5. Add constraints: constraints/ax7325b_10gbe_uart.xdc

6. Run synthesis and implementation

Quick Build Script

# Create project
create_project p31_10gbe_uart ./vivado_project -part xc7k325tffg900-2

# Add sources
add_files -norecurse {
    src/top/udp_10gbe_uart_top.v
    src/10gbe/udp_test.v
    src/10gbe/udp_read_write_ctrl.v
    src/10gbe/ax_debounce.v
    src/10gbe/axi_10g_ethernet_0_sync_reset.v
    src/10gbe/axi_10g_ethernet_0_axi_lite_sm.v
    src/uart/uart_tx.vhd
    src/btn/button_debouncer.vhd
    src/btn/edge_detector.vhd
    src/fifo/fifo.vhd
}

# Add IP repo
set_property ip_repo_paths {ip_repo} [current_project]
update_ip_catalog

# Add constraints
add_files -fileset constrs_1 -norecurse constraints/ax7325b_10gbe_uart.xdc

# Set top module
set_property top udp_10gbe_uart_top [current_fileset]

# Run build
launch_runs impl_1 -to_step write_bitstream -jobs 8

Testing

PC Setup

1. Configure network interface:

   sudo ip addr add 192.168.0.144/24 dev eth0
   sudo ip link set eth0 up

2. Connect SFP+ fiber (crossover: FPGA TX -> PC RX, FPGA RX -> PC TX)

3. Verify link:

   # Check LEDs: LED0-2 should be ON when link is up
   # LED3 will light after ARP exchange
   ping 192.168.0.215

UDP Loopback Test

# Terminal 1: Listen for echoed packets
nc -u -l 8080

# Terminal 2: Send test data
echo "Hello FPGA" | nc -u 192.168.0.215 8080

UART Debug

# Connect to UART (115200 8N1)
picocom -b 115200 /dev/ttyUSB0

# Press debug button on FPGA to see packet counts

Directory Structure

31-10gbe-uart-debug/
├── README.md
├── constraints/
│   └── ax7325b_10gbe_uart.xdc
├── docs/
├── ip_repo/
│   └── udp_ip_1.0/
│       └── hdl/
│           └── udp_top.v
├── scripts/
├── src/
│   ├── 10gbe/
│   │   ├── udp_test.v
│   │   ├── udp_read_write_ctrl.v
│   │   ├── ax_debounce.v
│   │   ├── axi_10g_ethernet_0_sync_reset.v
│   │   └── axi_10g_ethernet_0_axi_lite_sm.v
│   ├── btn/
│   │   ├── button_debouncer.vhd
│   │   └── edge_detector.vhd
│   ├── fifo/
│   │   └── fifo.vhd
│   ├── top/
│   │   └── udp_10gbe_uart_top.v
│   └── uart/
│       └── uart_tx.vhd
└── test/

Known Issues

1. Vivado IP Encryption: The ALINX UDP IP (alinx_udp_ip.vp) is encrypted with 2017 keys and require vendor IP license.

2. Mixed VHDL/Verilog: Vivado handles mixed HDL compilation, but ensure all VHDL files are properly listed in the project.

References

• AX7325B User Manual
• Xilinx 10G Ethernet Subsystem PG157
• ITCH 5.0 Protocol Specification

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Status: Development Created: January 2026 Author: Adilson Dias

Target Board: ALINX AX7325B (Kintex-7 XC7K325T-2FFG900I)