RTL implementation of the low latency ethernet modules for the NASDAQ HFT FPGA project.

RTL implementation of the ethernet physical layer PCS for 10GBASE-R and 40GBASE-R.

FPGA Low latency 10GBASE-R PCS

This project integrates the ALINX 10GbE UDP vendor design with a UART debug interface for monitoring network traffic and system status. It serves as the foundation for ITCH market data reception on the AX7325B (Kintex-7 XC7K325T) FPGA.

Order Book 10GbE - FPGA Order Book with UDP TX and Latency Measurement

A complete custom implementation of the 10GBASE-R Physical Layer (PHY) in VHDL. This implementation provides full control over the 10 Gigabit Ethernet physical layer without relying on encrypted vendor IP.

This project implements a 10 Gigabit Ethernet (10GbE) interface using the Kintex-7 GTX transceivers on the ALINX AX7325B board. It uses the open-source [verilog-ethernet](https://github.com/alexforencich/verilog-ethernet) library for the MAC/PHY layers.