Add PatternWithEnumTypeInNestedModule

tests/PatternWithEnumTypeInNestedModule/Makefile.in

@@ -0,0 +1,2 @@
+TOP_FILE := $(TEST_DIR)/top.sv
+TOP_MODULE := top

tests/PatternWithEnumTypeInNestedModule/main.cpp

@@ -0,0 +1,40 @@
+#include <iostream>
+#include <verilated_vcd_c.h>
+
+#define VL_DEBUG
+#include "Vtop.h"
+#include "verilated.h"
+
+static vluint64_t main_time = 0;
+
+double
+sc_time_stamp()
+{
+  return main_time;
+}
+
+int main (int argc, char **argv) {
+  Verilated::commandArgs(argc, argv);
+  Vtop *top = new Vtop();
+
+  Verilated::traceEverOn(true);
+  VerilatedVcdC* tfp = new VerilatedVcdC;
+  top->trace(tfp, 99);
+  tfp->open("dump.vcd");
+
+  while (!Verilated::gotFinish() && (main_time < 100)) {
+    top->eval();
+    tfp->dump(main_time);
+
+    main_time += 1;
+
+    std::cout << "time: " << main_time
+              << " o: " << (int)top->o
+              << std::endl;
+  }
+  top->final();
+  tfp->close();
+  delete top;
+
+  return 0;
+}

tests/PatternWithEnumTypeInNestedModule/top.sv

@@ -0,0 +1,48 @@
+module prim_subreg(output int a);
+   parameter logic [4:0] RESVAL = '0;
+   assign a = int'(RESVAL);
+endmodule // prim_subreg
+
+module prim_subreg_shadow(output int b);
+   typedef struct packed {
+      logic [2:0] a;
+      logic [1:0] b;
+   } struct_t;
+
+   typedef enum logic [2:0] {
+      ENUM_ITEM = 3'b000
+   } enum_t;
+
+   parameter struct_t RESVAL = '{
+      a: ENUM_ITEM,
+      b: '1
+   };
+
+   prim_subreg #(
+      .RESVAL(RESVAL)
+   ) staged_reg (.a(b));
+endmodule // prim_subreg_shadow
+
+module top(output int o);
+   typedef struct packed {
+      logic [1:0] a;
+      logic [2:0] b;
+   } struct_t;
+
+   typedef enum logic [1:0] {
+      ENUM_ITEM = 2'b11
+   } enum_t;
+
+   parameter struct_t CTRL_RESET = '{
+      a: ENUM_ITEM,
+      b: '0
+   };
+
+   prim_subreg_shadow #(
+      .RESVAL(CTRL_RESET)
+   ) u_ctrl_reg_shadowed (.b(o));
+
+   always_comb begin
+      assert(o == 24);
+   end
+endmodule // top

tests/PatternWithEnumTypeInNestedModule/yosys_script

@@ -0,0 +1,6 @@
+plugin -i uhdm
+read_uhdm -debug top.uhdm
+prep -top \top
+write_verilog
+write_verilog yosys.sv
+sim -rstlen 10 -vcd dump.vcd