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DCLS integration #737

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a7ce171
Bump VeeR core
kgugala Jan 30, 2025
b3d205d
Switch to use DCLS VeeR version
kgugala Jan 30, 2025
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4 changes: 3 additions & 1 deletion src/integration/config/caliptra_top_tb.vf
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Original file line number Diff line number Diff line change
Expand Up @@ -218,6 +218,7 @@ ${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/lib/axi4_to_ahb.sv
${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/lib/el2_lib.sv
${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/lib/mem_lib.sv
${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/lib/el2_mem_if.sv
${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/lib/el2_regfile_if.sv
${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/lsu/el2_lsu_addrcheck.sv
${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/lsu/el2_lsu_bus_buffer.sv
${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/lsu/el2_lsu_bus_intf.sv
Expand All @@ -234,6 +235,7 @@ ${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/el2_dma_ctrl.sv
${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/el2_pic_ctrl.sv
${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/el2_pmp.sv
${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/el2_veer.sv
${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/el2_veer_lockstep.sv
${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/el2_veer_wrapper.sv
${CALIPTRA_ROOT}/src/ahb_lite_bus/rtl/ahb_lite_bus_inf.sv
${CALIPTRA_ROOT}/src/ahb_lite_bus/rtl/ahb_lite_address_decoder.sv
Expand Down Expand Up @@ -621,4 +623,4 @@ ${CALIPTRA_ROOT}/src/csrng/rtl/csrng_block_encrypt.sv
${CALIPTRA_ROOT}/src/csrng/rtl/csrng_state_db.sv
${CALIPTRA_ROOT}/src/csrng/rtl/csrng_cmd_stage.sv
${CALIPTRA_ROOT}/src/csrng/rtl/csrng.sv
${CALIPTRA_ROOT}/src/integration/rtl/caliptra_top.sv
${CALIPTRA_ROOT}/src/integration/rtl/caliptra_top.sv
6 changes: 4 additions & 2 deletions src/integration/rtl/caliptra_reg.h
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Expand Up @@ -9650,8 +9650,10 @@
#define SOC_IFC_REG_CPTRA_HW_ERROR_FATAL_NMI_PIN_MASK (0x4)
#define SOC_IFC_REG_CPTRA_HW_ERROR_FATAL_CRYPTO_ERR_LOW (3)
#define SOC_IFC_REG_CPTRA_HW_ERROR_FATAL_CRYPTO_ERR_MASK (0x8)
#define SOC_IFC_REG_CPTRA_HW_ERROR_FATAL_RSVD_LOW (4)
#define SOC_IFC_REG_CPTRA_HW_ERROR_FATAL_RSVD_MASK (0xfffffff0)
#define SOC_IFC_REG_CPTRA_HW_ERROR_FATAL_DCLS_ERROR_LOW (4)
#define SOC_IFC_REG_CPTRA_HW_ERROR_FATAL_DCLS_ERROR_MASK (0x10)
#define SOC_IFC_REG_CPTRA_HW_ERROR_FATAL_RSVD_LOW (5)
#define SOC_IFC_REG_CPTRA_HW_ERROR_FATAL_RSVD_MASK (0xffffffe0)
#endif
#define CLP_SOC_IFC_REG_CPTRA_HW_ERROR_NON_FATAL (0x30030004)
#ifndef SOC_IFC_REG_CPTRA_HW_ERROR_NON_FATAL
Expand Down
6 changes: 4 additions & 2 deletions src/integration/rtl/caliptra_reg_field_defines.svh
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Expand Up @@ -7691,8 +7691,10 @@
`define SOC_IFC_REG_CPTRA_HW_ERROR_FATAL_NMI_PIN_MASK (32'h4)
`define SOC_IFC_REG_CPTRA_HW_ERROR_FATAL_CRYPTO_ERR_LOW (3)
`define SOC_IFC_REG_CPTRA_HW_ERROR_FATAL_CRYPTO_ERR_MASK (32'h8)
`define SOC_IFC_REG_CPTRA_HW_ERROR_FATAL_RSVD_LOW (4)
`define SOC_IFC_REG_CPTRA_HW_ERROR_FATAL_RSVD_MASK (32'hfffffff0)
`define SOC_IFC_REG_CPTRA_HW_ERROR_FATAL_DCLS_ERROR_LOW (4)
`define SOC_IFC_REG_CPTRA_HW_ERROR_FATAL_DCLS_ERROR_MASK (32'h10)
`define SOC_IFC_REG_CPTRA_HW_ERROR_FATAL_RSVD_LOW (5)
`define SOC_IFC_REG_CPTRA_HW_ERROR_FATAL_RSVD_MASK (32'hffffffe0)
`endif
`ifndef SOC_IFC_REG_CPTRA_HW_ERROR_NON_FATAL
`define SOC_IFC_REG_CPTRA_HW_ERROR_NON_FATAL (32'h4)
Expand Down
15 changes: 15 additions & 0 deletions src/integration/rtl/caliptra_top.sv
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Expand Up @@ -439,6 +439,12 @@ always_comb begin
el2_icache_stub.ic_tag_data_raw_pre = '0;
end

logic cptra_panic;

`ifndef RV_LOCKSTEP_ENABLE
assign cptra_panic = 1'b0;
`endif

el2_veer_wrapper rvtop (
`ifdef CALIPTRA_FORCE_CPU_RESET
.rst_l ( 1'b0 ),
Expand Down Expand Up @@ -577,6 +583,13 @@ el2_veer_wrapper rvtop (
// Caliptra Memory Export Interface
.el2_mem_export (el2_mem_export),

`ifdef RV_LOCKSTEP_ENABLE
// Shadow Core control
.disable_corruption_detection_i(1'b0),
.lockstep_err_injection_en_i(1'b0),
.corruption_detected_o(cptra_panic),
`endif

.core_id ('0),
.scan_mode ( scan_mode ), // To enable scan mode
.mbist_mode ( 1'b0 ) // to enable mbist
Expand Down Expand Up @@ -1359,6 +1372,8 @@ soc_ifc_top1
.fw_update_rst_window(fw_update_rst_window),
//multiple cryptos operating at once, assert fatal error
.crypto_error(crypto_error),
// DCLS error
.dcls_error (cptra_panic ),
//caliptra uncore jtag ports
.cptra_uncore_dmi_reg_en( cptra_uncore_dmi_reg_en ),
.cptra_uncore_dmi_reg_wr_en( cptra_uncore_dmi_reg_wr_en ),
Expand Down
1 change: 1 addition & 0 deletions src/integration/rtl/config_defines.svh
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Expand Up @@ -100,6 +100,7 @@
`define CALIPTRA_RV_TOP `CALIPTRA_TOP.caliptra_top_dut

`define RV_TOP `CALIPTRA_RV_TOP.rvtop
`define RV_LOCKSTEP_ENABLE 1

`define CALIPTRA_ICG cptra_clk_gate

Expand Down
2 changes: 2 additions & 0 deletions src/riscv_core/veer_el2/config/compile.yml
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Expand Up @@ -54,6 +54,7 @@ targets:
- $COMPILE_ROOT/rtl/lib/el2_lib.sv
- $COMPILE_ROOT/rtl/lib/mem_lib.sv
- $COMPILE_ROOT/rtl/lib/el2_mem_if.sv
- $COMPILE_ROOT/rtl/lib/el2_regfile_if.sv
- $COMPILE_ROOT/rtl/lsu/el2_lsu_addrcheck.sv
- $COMPILE_ROOT/rtl/lsu/el2_lsu_bus_buffer.sv
- $COMPILE_ROOT/rtl/lsu/el2_lsu_bus_intf.sv
Expand All @@ -70,6 +71,7 @@ targets:
- $COMPILE_ROOT/rtl/el2_pic_ctrl.sv
- $COMPILE_ROOT/rtl/el2_pmp.sv
- $COMPILE_ROOT/rtl/el2_veer.sv
- $COMPILE_ROOT/rtl/el2_veer_lockstep.sv
- $COMPILE_ROOT/rtl/el2_veer_wrapper.sv
tops: [el2_veer_wrapper]
rtl_lint:
Expand Down
4 changes: 3 additions & 1 deletion src/riscv_core/veer_el2/config/el2_veer_wrapper.vf
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Expand Up @@ -33,6 +33,7 @@ ${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/lib/axi4_to_ahb.sv
${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/lib/el2_lib.sv
${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/lib/mem_lib.sv
${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/lib/el2_mem_if.sv
${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/lib/el2_el2_regfile_if.sv
${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/lsu/el2_lsu_addrcheck.sv
${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/lsu/el2_lsu_bus_buffer.sv
${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/lsu/el2_lsu_bus_intf.sv
Expand All @@ -49,4 +50,5 @@ ${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/el2_dma_ctrl.sv
${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/el2_pic_ctrl.sv
${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/el2_pmp.sv
${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/el2_veer.sv
${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/el2_veer_wrapper.sv
${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/el2_veer_lockstep.sv
${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/el2_veer_wrapper.sv
3 changes: 3 additions & 0 deletions src/riscv_core/veer_el2/rtl/common_defines.sv
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Expand Up @@ -244,6 +244,9 @@
`define RV_INST_ACCESS_MASK5 'hffffffff
`define RV_INST_ACCESS_MASK6 'hffffffff
`define RV_INST_ACCESS_MASK7 'hffffffff
`define RV_LOCKSTEP_DELAY 3
`define RV_LOCKSTEP_ENABLE 1
`define RV_LOCKSTEP_REGFILE_ENABLE 1
`define RV_PMP_ENTRIES 64
`define REGWIDTH 32
`define RV_RESET_VEC 'h00000000
Expand Down
44 changes: 43 additions & 1 deletion src/riscv_core/veer_el2/rtl/dec/el2_dec.sv
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Expand Up @@ -327,6 +327,10 @@ module el2_dec
output logic dec_tlu_dccm_clk_override, // override DCCM clock domain gating
output logic dec_tlu_icm_clk_override, // override ICCM clock domain gating

`ifdef RV_LOCKSTEP_REGFILE_ENABLE
el2_regfile_if.veer_rf_src regfile,
`endif

output logic dec_tlu_i0_commit_cmt, // committed i0 instruction
// Excluding scan_mode from coverage as its usage is determined by the integrator of the VeeR core.
/*pragma coverage off*/
Expand Down Expand Up @@ -429,14 +433,52 @@ module el2_dec

el2_dec_decode_ctl #(.pt(pt)) decode (.*);

`ifdef RV_LOCKSTEP_REGFILE_ENABLE
el2_regfile_if regfile_if ();
assign regfile.gpr.ra = regfile_if.gpr.ra;
assign regfile.gpr.sp = regfile_if.gpr.sp;
assign regfile.gpr.fp = regfile_if.gpr.fp;
assign regfile.gpr.a0 = regfile_if.gpr.a0;
assign regfile.gpr.a1 = regfile_if.gpr.a1;
assign regfile.gpr.a2 = regfile_if.gpr.a2;
assign regfile.gpr.a3 = regfile_if.gpr.a3;
assign regfile.gpr.a4 = regfile_if.gpr.a4;
assign regfile.gpr.a5 = regfile_if.gpr.a5;
assign regfile.gpr.a6 = regfile_if.gpr.a6;
assign regfile.gpr.a7 = regfile_if.gpr.a7;

assign regfile.tlu.pc = regfile_if.tlu.pc;
assign regfile.tlu.npc = regfile_if.tlu.npc;
assign regfile.tlu.mstatus = regfile_if.tlu.mstatus;
assign regfile.tlu.mie = regfile_if.tlu.mie;
assign regfile.tlu.mtvec = regfile_if.tlu.mtvec;
assign regfile.tlu.mscratch = regfile_if.tlu.mscratch;
assign regfile.tlu.mepc = regfile_if.tlu.mepc;
assign regfile.tlu.mcause = regfile_if.tlu.mcause;
assign regfile.tlu.mtval = regfile_if.tlu.mtval;
assign regfile.tlu.mip = regfile_if.tlu.mip;
assign regfile.tlu.mcyclel = regfile_if.tlu.mcyclel;
assign regfile.tlu.mcycleh = regfile_if.tlu.mcycleh;
assign regfile.tlu.minstretl = regfile_if.tlu.minstretl;
assign regfile.tlu.minstreth = regfile_if.tlu.minstreth;
assign regfile.tlu.mrac = regfile_if.tlu.mrac;
`endif

el2_dec_tlu_ctl #(.pt(pt)) tlu (.*);
el2_dec_tlu_ctl #(.pt(pt)
) tlu (
`ifdef RV_LOCKSTEP_REGFILE_ENABLE
.regfile(regfile_if.veer_tlu_rf),
`endif
.*);


el2_dec_gpr_ctl #(
.pt(pt)
) arf (
.*,
`ifdef RV_LOCKSTEP_REGFILE_ENABLE
.regfile(regfile_if.veer_gpr_rf),
`endif
// inputs
.raddr0(dec_i0_rs1_d[4:0]),
.raddr1(dec_i0_rs2_d[4:0]),
Expand Down
18 changes: 18 additions & 0 deletions src/riscv_core/veer_el2/rtl/dec/el2_dec_gpr_ctl.sv
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Expand Up @@ -39,6 +39,10 @@ import el2_pkg::*;
output logic [31:0] rd0, // read data
output logic [31:0] rd1,

`ifdef RV_LOCKSTEP_REGFILE_ENABLE
el2_regfile_if.veer_gpr_rf regfile,
`endif

// Excluding scan_mode from coverage as its usage is determined by the integrator of the VeeR core.
/*pragma coverage off*/
input logic scan_mode
Expand All @@ -50,6 +54,20 @@ import el2_pkg::*;
logic [31:1] w0v,w1v,w2v;
logic [31:1] gpr_wr_en;

`ifdef RV_LOCKSTEP_REGFILE_ENABLE
assign regfile.gpr.ra = gpr_out[1][31:0]; // x1
assign regfile.gpr.sp = gpr_out[2][31:0]; // x2
assign regfile.gpr.fp = gpr_out[8][31:0]; // x8
assign regfile.gpr.a0 = gpr_out[10][31:0]; // x10
assign regfile.gpr.a1 = gpr_out[11][31:0]; // x11
assign regfile.gpr.a2 = gpr_out[12][31:0]; // x12
assign regfile.gpr.a3 = gpr_out[13][31:0]; // x13
assign regfile.gpr.a4 = gpr_out[14][31:0]; // x14
assign regfile.gpr.a5 = gpr_out[15][31:0]; // x15
assign regfile.gpr.a6 = gpr_out[16][31:0]; // x16
assign regfile.gpr.a7 = gpr_out[17][31:0]; // x17
`endif

// GPR Write Enables
assign gpr_wr_en[31:1] = (w0v[31:1] | w1v[31:1] | w2v[31:1]);
for ( genvar j=1; j<32; j++ ) begin : gpr
Expand Down
72 changes: 54 additions & 18 deletions src/riscv_core/veer_el2/rtl/dec/el2_dec_tlu_ctl.sv
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Expand Up @@ -247,6 +247,10 @@ import el2_pkg::*;
output logic dec_tlu_dccm_clk_override, // override DCCM clock domain gating
output logic dec_tlu_icm_clk_override, // override ICCM clock domain gating

`ifdef RV_LOCKSTEP_REGFILE_ENABLE
el2_regfile_if.veer_tlu_rf regfile,
`endif

`ifdef RV_USER_MODE

// Privilege mode
Expand Down Expand Up @@ -2919,6 +2923,25 @@ assign dec_csr_legal_d = ( dec_csr_any_unq_d &
~(dec_csr_wen_unq_d & (csr_mvendorid | csr_marchid | csr_mimpid | csr_mhartid | csr_mdseac | csr_meihap)) // that's not a write to a RO CSR
);
// CSR read mux
logic [31:0] mstatus_rf, mie_rf, mtvec_rf, mscratch_rf, mepc_rf, mcause_rf, mtval_rf, mip_rf, mcyclel_rf, mcycleh_rf, minstretl_rf, minstreth_rf, mrac_rf;
`ifdef RV_USER_MODE
assign mstatus_rf = {14'b0, mstatus[MSTATUS_MPRV], 4'b0, ~mstatus[MSTATUS_MPP], ~mstatus[MSTATUS_MPP], 3'b0, mstatus[MSTATUS_MPIE], 3'b0, mstatus[MSTATUS_MIE], 3'b0};
`else
assign mstatus_rf = {19'b0, 2'b11, 3'b0, mstatus[MSTATUS_MPIE], 3'b0, mstatus[MSTATUS_MIE], 3'b0};
`endif
assign mie_rf = {1'b0, mie[5:3], 16'b0, mie[2], 3'b0, mie[1], 3'b0, mie[0], 3'b0};
assign mtvec_rf = {mtvec[30:1], 1'b0, mtvec[0]};
assign mscratch_rf = mscratch[31:0];
assign mepc_rf = {mepc[31:1], 1'b0};
assign mcause_rf = mcause[31:0];
assign mtval_rf = mtval[31:0];
assign mip_rf = {1'b0, mip[5:3], 16'b0, mip[2], 3'b0, mip[1], 3'b0, mip[0], 3'b0};
assign mcyclel_rf = mcyclel[31:0];
assign mcycleh_rf = mcycleh_inc[31:0];
assign minstretl_rf = minstretl_read[31:0];
assign minstreth_rf = minstreth_read[31:0];
assign mrac_rf = mrac[31:0];

assign dec_csr_rddata_d[31:0] = (
`ifdef RV_USER_MODE
({32{csr_misa}} & 32'h40101104) |
Expand All @@ -2929,24 +2952,20 @@ assign dec_csr_rddata_d[31:0] = (
({32{csr_marchid}} & 32'h00000010) |
({32{csr_mimpid}} & 32'h4) |
({32{csr_mhartid}} & {core_id[31:4], 4'b0}) |
`ifdef RV_USER_MODE
({32{csr_mstatus}} & {14'b0, mstatus[MSTATUS_MPRV], 4'b0, ~mstatus[MSTATUS_MPP], ~mstatus[MSTATUS_MPP], 3'b0, mstatus[MSTATUS_MPIE], 3'b0, mstatus[MSTATUS_MIE], 3'b0}) |
`else
({32{csr_mstatus}} & {19'b0, 2'b11, 3'b0, mstatus[MSTATUS_MPIE], 3'b0, mstatus[MSTATUS_MIE], 3'b0}) |
`endif
({32{csr_mtvec}} & {mtvec[30:1], 1'b0, mtvec[0]}) |
({32{csr_mip}} & {1'b0, mip[5:3], 16'b0, mip[2], 3'b0, mip[1], 3'b0, mip[0], 3'b0}) |
({32{csr_mie}} & {1'b0, mie[5:3], 16'b0, mie[2], 3'b0, mie[1], 3'b0, mie[0], 3'b0}) |
({32{csr_mcyclel}} & mcyclel[31:0]) |
({32{csr_mcycleh}} & mcycleh_inc[31:0]) |
({32{csr_minstretl}} & minstretl_read[31:0]) |
({32{csr_minstreth}} & minstreth_read[31:0]) |
({32{csr_mscratch}} & mscratch[31:0]) |
({32{csr_mepc}} & {mepc[31:1], 1'b0}) |
({32{csr_mcause}} & mcause[31:0]) |
({32{csr_mstatus}} & mstatus_rf[31:0]) |
({32{csr_mtvec}} & mtvec_rf) |
({32{csr_mip}} & mip_rf) |
({32{csr_mie}} & mie_rf) |
({32{csr_mcyclel}} & mcyclel_rf) |
({32{csr_mcycleh}} & mcycleh_rf) |
({32{csr_minstretl}} & minstretl_rf) |
({32{csr_minstreth}} & minstreth_rf) |
({32{csr_mscratch}} & mscratch_rf) |
({32{csr_mepc}} & mepc_rf) |
({32{csr_mcause}} & mcause_rf) |
({32{csr_mscause}} & {28'b0, mscause[3:0]}) |
({32{csr_mtval}} & mtval[31:0]) |
({32{csr_mrac}} & mrac[31:0]) |
({32{csr_mtval}} & mtval_rf) |
({32{csr_mrac}} & mrac_rf) |
({32{csr_mdseac}} & mdseac[31:0]) |
({32{csr_meivt}} & {meivt[31:10], 10'b0}) |
({32{csr_meihap}} & {meivt[31:10], meihap[9:2], 2'b0}) |
Expand Down Expand Up @@ -3006,7 +3025,24 @@ assign dec_csr_rddata_d[31:0] = (
({32{dec_pmp_read_d}} & dec_pmp_rddata_d[31:0])
);


`ifdef RV_LOCKSTEP_REGFILE_ENABLE
// Expose the register file
assign regfile.tlu.pc = pc_r;
assign regfile.tlu.npc = npc_r;
assign regfile.tlu.mstatus = mstatus_rf;
assign regfile.tlu.mie = mie_rf;
assign regfile.tlu.mtvec = mtvec_rf;
assign regfile.tlu.mscratch = mscratch_rf;
assign regfile.tlu.mepc = mepc_rf;
assign regfile.tlu.mcause = mcause_rf;
assign regfile.tlu.mtval = mtval_rf;
assign regfile.tlu.mip = mip_rf;
assign regfile.tlu.mcyclel = mcyclel_rf;
assign regfile.tlu.mcycleh = mcycleh_rf;
assign regfile.tlu.minstretl = minstretl_rf;
assign regfile.tlu.minstreth = minstreth_rf;
assign regfile.tlu.mrac = mrac_rf;
`endif

endmodule // el2_dec_tlu_ctl

Expand Down
1 change: 1 addition & 0 deletions src/riscv_core/veer_el2/rtl/el2_mem.sv
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Expand Up @@ -161,6 +161,7 @@ else begin
assign ictag_debug_rd_data = '0 ;
assign ic_debug_rd_data = '0 ;
assign ic_eccerr = '0;
assign ic_parerr = '0;
end // else: !if( pt.ICACHE_ENABLE )


Expand Down
3 changes: 3 additions & 0 deletions src/riscv_core/veer_el2/rtl/el2_param.vh
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Expand Up @@ -167,6 +167,9 @@ parameter el2_param_t pt = '{
INST_ACCESS_MASK6 : 36'h0FFFFFFFF ,
INST_ACCESS_MASK7 : 36'h0FFFFFFFF ,
LOAD_TO_USE_PLUS1 : 5'h00 ,
LOCKSTEP_DELAY : 7'h03 ,
LOCKSTEP_ENABLE : 5'h01 ,
LOCKSTEP_REGFILE_ENABLE : 5'h01 ,
LSU2DMA : 5'h00 ,
LSU_BUS_ID : 5'h01 ,
LSU_BUS_PRTY : 6'h02 ,
Expand Down
3 changes: 3 additions & 0 deletions src/riscv_core/veer_el2/rtl/el2_pdef.vh
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Expand Up @@ -168,6 +168,9 @@ typedef struct packed {
logic [35:0] INST_ACCESS_MASK6;
logic [35:0] INST_ACCESS_MASK7;
logic [4:0] LOAD_TO_USE_PLUS1;
logic [6:0] LOCKSTEP_DELAY;
logic [4:0] LOCKSTEP_ENABLE;
logic [4:0] LOCKSTEP_REGFILE_ENABLE;
logic [4:0] LSU2DMA;
logic [4:0] LSU_BUS_ID;
logic [5:0] LSU_BUS_PRTY;
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2 changes: 2 additions & 0 deletions src/riscv_core/veer_el2/rtl/el2_pic_ctrl.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -402,8 +402,10 @@ if (pt.PIC_2CYCLE == 1) begin : genblock
end
else begin : genblock

/* pragma coverage off*/
logic [NUM_LEVELS:0] [pt.PIC_TOTAL_INT_PLUS1+1:0] [INTPRIORITY_BITS-1:0] level_intpend_w_prior_en;
logic [NUM_LEVELS:0] [pt.PIC_TOTAL_INT_PLUS1+1:0] [ID_BITS-1:0] level_intpend_id;
/* pragma coverage on*/

assign level_intpend_w_prior_en[0][pt.PIC_TOTAL_INT_PLUS1+1:0] = {{2*INTPRIORITY_BITS{1'b0}},intpend_w_prior_en[pt.PIC_TOTAL_INT_PLUS1-1:0]} ;
assign level_intpend_id[0][pt.PIC_TOTAL_INT_PLUS1+1:0] = {{2*ID_BITS{1'b1}},intpend_id[pt.PIC_TOTAL_INT_PLUS1-1:0]} ;
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