[DOC] Clarify min clock frequency requirement#1011
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Clarified minimum operating clock frequency requirements for I3C core.
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Pull request overview
This PR clarifies the minimum clock frequency requirement for the Caliptra Subsystem by adding a note explaining the assumptions behind the 333 MHz calculation. The addition helps SoC integrators understand that the minimum frequency was calculated assuming zero delay to and from the SCL/SDA pads, and that actual implementations with significant pad timing delays may require higher clock frequencies.
- Adds clarification about the zero-delay assumption in the 333 MHz minimum frequency calculation
- Provides guidance for SoCs with large timing delays
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calebofearth
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Jan 7, 2026
Nitsirks
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Jan 7, 2026
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…12, 1125, 1129, 1143, 1144) (#1149) * [Cherry-pick] [DOC] RDC constraint and version update (#922) * [Cherry-pick] [DOC] Clarify min clock frequency requirement (#1011) * Update clock frequency requirements in specification Clarified minimum operating clock frequency requirements for I3C core. * Correct timing reference in clock frequency section * [Cherry-pick] [DOC] Update I3C core integration details (#1012) * [Cherry-pick] [DOC] Strap and reset clarifications (#1125) * update reset requirement to be consistent update strap signals with requirement details for driving before reset de-assertion * MICROSOFT AUTOMATED PIPELINE: Stamp 'user/dev/michnorris/doc_updates' with updated timestamp and hash after successful run --------- Co-authored-by: EMRE KARABULUT <63821295+ekarabu@users.noreply.github.com> * [Cherry-pick] Document LCC token fuse provisioning for HKMS (#1129) Extend the Token Validation python code block to show the full cSHAKE128 hashing workflow with byte-arrays: - Show raw token as little-endian byte-array input - Show hashed token as byte-array output for HKMS to provision into SECRET_LC_TRANSITION_PARTITION fuses - Fix TOKEN_OFFSET word ordering (was misordered for OFFSET 1 and 2) to match RTL register mapping - Fix 'Toke' typo to 'Token' Co-authored-by: Copilot <223556219+Copilot@users.noreply.github.com> * [Cherry-pick] [DOC] Revise explanatory language about I3C core frequency requirements and CDC (#1143) Updated the required frequency for I3C core operation and clarified the change from a 170 MHz clock due to CDC issues. Added references to discussions about CDC violations. * [Cherry-pick] [DOC] Clarify connection requirement for AXI additional signals (#1144) * Clarify connection requirement for AXI additional signals * Update AXI signal specifications in documentation Clarify unused AXI signals and their role in the Caliptra Subsystem. Provide details on AXI USER width and ID width requirements. --------- Co-authored-by: pjangid30 <pjangid@nvidia.com> Co-authored-by: Clayton Kuchta <ckuchta@microsoft.com> Co-authored-by: EMRE KARABULUT <63821295+ekarabu@users.noreply.github.com> Co-authored-by: Copilot <223556219+Copilot@users.noreply.github.com>
dharamvir-nxp
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Jun 15, 2026
* Update clock frequency requirements in specification Clarified minimum operating clock frequency requirements for I3C core. * Correct timing reference in clock frequency section
calebofearth
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* Update clock frequency requirements in specification Clarified minimum operating clock frequency requirements for I3C core. * Correct timing reference in clock frequency section
calebofearth
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Jun 17, 2026
…29, 1125, 1143, 1144) (#1155) * [Cherry-pick] document update for LCC and FC (#641) * document update for LCC and FC * update state trans diagram This cherry-pick commit also includes clarification language from #1152 * [Cherry-pick] [DOC] Clarify min clock frequency requirement (#1011) * Update clock frequency requirements in specification Clarified minimum operating clock frequency requirements for I3C core. * Correct timing reference in clock frequency section * [Cherry-pick][DOC] Document LCC token fuse provisioning for HKMS (#1129) Extend the Token Validation python code block to show the full cSHAKE128 hashing workflow with byte-arrays: - Show raw token as little-endian byte-array input - Show hashed token as byte-array output for HKMS to provision into SECRET_LC_TRANSITION_PARTITION fuses - Fix TOKEN_OFFSET word ordering (was misordered for OFFSET 1 and 2) to match RTL register mapping - Fix 'Toke' typo to 'Token' Co-authored-by: Copilot <223556219+Copilot@users.noreply.github.com> * [Cherry-pick][DOC] Strap and reset clarifications (#1125) * update reset requirement to be consistent update strap signals with requirement details for driving before reset de-assertion * MICROSOFT AUTOMATED PIPELINE: Stamp 'user/dev/michnorris/doc_updates' with updated timestamp and hash after successful run --------- Co-authored-by: EMRE KARABULUT <63821295+ekarabu@users.noreply.github.com> * [Cherry-pick][DOC] Revise explanatory language about I3C core frequency requirements and CDC (#1143) Updated the required frequency for I3C core operation and clarified the change from a 170 MHz clock due to CDC issues. Added references to discussions about CDC violations. * [Cherry-pick][DOC] Clarify connection requirement for AXI additional signals (#1144) * Clarify connection requirement for AXI additional signals * Update AXI signal specifications in documentation Clarify unused AXI signals and their role in the Caliptra Subsystem. Provide details on AXI USER width and ID width requirements. --------- Co-authored-by: EMRE KARABULUT <63821295+ekarabu@users.noreply.github.com> Co-authored-by: Copilot <223556219+Copilot@users.noreply.github.com> Co-authored-by: Michael Norris <108370498+Nitsirks@users.noreply.github.com>
kgugala
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Jun 24, 2026
…29, 1125, 1143, 1144) (chipsalliance#1155) * [Cherry-pick] document update for LCC and FC (chipsalliance#641) * document update for LCC and FC * update state trans diagram This cherry-pick commit also includes clarification language from chipsalliance#1152 * [Cherry-pick] [DOC] Clarify min clock frequency requirement (chipsalliance#1011) * Update clock frequency requirements in specification Clarified minimum operating clock frequency requirements for I3C core. * Correct timing reference in clock frequency section * [Cherry-pick][DOC] Document LCC token fuse provisioning for HKMS (chipsalliance#1129) Extend the Token Validation python code block to show the full cSHAKE128 hashing workflow with byte-arrays: - Show raw token as little-endian byte-array input - Show hashed token as byte-array output for HKMS to provision into SECRET_LC_TRANSITION_PARTITION fuses - Fix TOKEN_OFFSET word ordering (was misordered for OFFSET 1 and 2) to match RTL register mapping - Fix 'Toke' typo to 'Token' Co-authored-by: Copilot <223556219+Copilot@users.noreply.github.com> * [Cherry-pick][DOC] Strap and reset clarifications (chipsalliance#1125) * update reset requirement to be consistent update strap signals with requirement details for driving before reset de-assertion * MICROSOFT AUTOMATED PIPELINE: Stamp 'user/dev/michnorris/doc_updates' with updated timestamp and hash after successful run --------- Co-authored-by: EMRE KARABULUT <63821295+ekarabu@users.noreply.github.com> * [Cherry-pick][DOC] Revise explanatory language about I3C core frequency requirements and CDC (chipsalliance#1143) Updated the required frequency for I3C core operation and clarified the change from a 170 MHz clock due to CDC issues. Added references to discussions about CDC violations. * [Cherry-pick][DOC] Clarify connection requirement for AXI additional signals (chipsalliance#1144) * Clarify connection requirement for AXI additional signals * Update AXI signal specifications in documentation Clarify unused AXI signals and their role in the Caliptra Subsystem. Provide details on AXI USER width and ID width requirements. --------- Co-authored-by: EMRE KARABULUT <63821295+ekarabu@users.noreply.github.com> Co-authored-by: Copilot <223556219+Copilot@users.noreply.github.com> Co-authored-by: Michael Norris <108370498+Nitsirks@users.noreply.github.com>
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Mention min freq was calculated based on 0 delay to and from the SCL/SDA pads.