add HasExtModuleDefine.define for creating ProbeType in BlackBox #3486
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| */ | ||
| def define[T <: chisel3.Element](tpe: T, path: Seq[String]): T = { | ||
| setInline( | ||
| s"firrtl_abi_definition_${path.mkString("_")}.sv", |
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Aw, this is what ref statements were intended for. They're not really used so no worries, the verilog ABI files is what we have!
The filename (and portion after "ref_" in the define) have specific rules, should these be automatically populated based on the circuit / module (def?) names?
Ports of ref type shall be lowered to a Verilog macro of the form
`define ref_<circuit name>_<module name>_<portname> <internal path from module>in a
file with nameref_<circuit name>_<module name>.sv.
These need to be output ports, and maybe if we're teaching Chisel about ABI either user is entirely responsible or we would do the necessary handling for aggregates/names?
Anyway, fly-by, just some thoughts!
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Thanks! I'll be too busy next week, I'm drafting and using this API in https://github.com/sequencer/riscv-cosim. After I think this API is good enough I'll be back to upstream to Chisel.
Contributor Checklist
docs/src?Type of Improvement
Desired Merge Strategy
Release Notes
Add HasExtModuleDefine.
Reviewer Checklist (only modified by reviewer)
3.5.x,3.6.x, or5.xdepending on impact, API modification or big change:6.0)?Enable auto-merge (squash), clean up the commit message, and label withPlease Merge.Create a merge commit.