Create method for marking all ports of a Module with DontTouchAnnotation

core/src/main/scala/chisel3/dontTouch.scala

@@ -2,10 +2,11 @@
 
 package chisel3
 
-import chisel3.experimental.{annotate, requireIsHardware, ChiselAnnotation}
+import chisel3.experimental.{annotate, requireIsHardware, BaseModule, ChiselAnnotation, ChiselMultiAnnotation}
 import chisel3.properties.Property
 import chisel3.reflect.DataMirror
 import firrtl.transforms.DontTouchAnnotation
+import firrtl.annotations.Annotation
 
 /** Marks that a signal's leaves are an optimization barrier to Chisel and the
   * FIRRTL compiler. This has the effect of guaranteeing that a signal will not
@@ -46,4 +47,18 @@ object dontTouch {
     data
   }
 
+  /** Mark a module so that its ports will not get optimized away.
+    *
+    * @param module whose ports shouldl not get optimized away
+    */
+  def modulePorts(module: BaseModule): BaseModule = {
+
+    annotate(new ChiselMultiAnnotation {
+      def toFirrtl: Seq[Annotation] = (DataMirror.fullModulePorts(module).map {
+        case (_, data) => DontTouchAnnotation(data.toNamed)
+      })
+    })
+    module
+  }
+
 }

src/test/scala/chiselTests/DontTouchSpec.scala

@@ -123,4 +123,66 @@ class DontTouchSpec extends ChiselFlatSpec with Utils {
     // Ensure can compile the result.
     compile(new HasProbesAndProperties())
   }
+
+  "dontTouch.modulePorts" should "mark all ports of a module" in {
+    class ModuleWithPorts extends Module {
+      val io = IO(new Bundle {
+        val a = Output(UInt(32.W))
+        val b = Input(new Bundle {
+          val x = Bool()
+          val y = new Bundle {
+            val foo = UInt(4.W)
+          }
+        })
+      })
+      io.a := DontCare
+    }
+    class DummyWrapper extends Module {
+      val dut = Module(new ModuleWithPorts)
+      dontTouch.modulePorts(dut)
+    }
+
+    val (_, annos) = getFirrtlAndAnnos(new DummyWrapper)
+    (annos should contain).allOf(
+      DontTouchAnnotation("~DummyWrapper|ModuleWithPorts>clock".rt),
+      DontTouchAnnotation("~DummyWrapper|ModuleWithPorts>reset".rt),
+      DontTouchAnnotation("~DummyWrapper|ModuleWithPorts>io".rt),
+      DontTouchAnnotation("~DummyWrapper|ModuleWithPorts>io.b".rt),
+      DontTouchAnnotation("~DummyWrapper|ModuleWithPorts>io.b.y".rt),
+      DontTouchAnnotation("~DummyWrapper|ModuleWithPorts>io.b.y.foo".rt),
+      DontTouchAnnotation("~DummyWrapper|ModuleWithPorts>io.b.x".rt),
+      DontTouchAnnotation("~DummyWrapper|ModuleWithPorts>io.a".rt)
+    )
+  }
+
+  "dontTouch.modulePorts" should "mark bored ports" in {
+    class ModuleToBore extends Module {
+      val io = IO(new Bundle {
+        val a = Output(UInt(32.W))
+        val b = Input(Bool())
+      })
+      io.a := DontCare
+
+      val boreMe = Wire(UInt(4.W))
+      boreMe := DontCare
+    }
+    class BoreModule extends Module {
+      val boreOut = IO(Output(UInt(4.W)))
+      val dut = Module(new ModuleToBore)
+
+      boreOut := chisel3.util.experimental.BoringUtils.bore(dut.boreMe)
+      dontTouch.modulePorts(dut)
+    }
+
+    val (_, annos) = getFirrtlAndAnnos(new BoreModule)
+    (annos should contain).allOf(
+      DontTouchAnnotation("~BoreModule|ModuleToBore>clock".rt),
+      DontTouchAnnotation("~BoreModule|ModuleToBore>reset".rt),
+      DontTouchAnnotation("~BoreModule|ModuleToBore>io".rt),
+      DontTouchAnnotation("~BoreModule|ModuleToBore>io.b".rt),
+      DontTouchAnnotation("~BoreModule|ModuleToBore>io.a".rt),
+      DontTouchAnnotation("~BoreModule|BoreModule>dut.boreOut_bore".rt)
+    )
+  }
+
 }