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Use DedupGroup Phase in ChiselStage$ #4728

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Use DedupGroup Phase in ChiselStage$ #4728

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2b3de20
Use DedupGroup Phase in ChiselStage$
seldridge Feb 25, 2025
c434130
fixup! Use DedupGroup Phase in ChiselStage$
seldridge Feb 25, 2025
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1 change: 1 addition & 0 deletions src/main/scala/circt/stage/ChiselStage.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -57,6 +57,7 @@ object ChiselStage {
Seq(
Dependency[chisel3.stage.phases.Elaborate],
Dependency[chisel3.stage.phases.Convert],
Dependency[chisel3.stage.phases.AddDedupGroupAnnotations],
Dependency[circt.stage.phases.AddImplicitOutputFile],
Dependency[chisel3.stage.phases.AddImplicitOutputAnnotationFile],
Dependency[circt.stage.phases.Checks],
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12 changes: 10 additions & 2 deletions src/test/scala-2/chiselTests/DedupSpec.scala
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Expand Up @@ -3,10 +3,11 @@
package chiselTests

import chisel3._
import chisel3.util._
import chisel3.util.{Counter, Decoupled, Queue}
import chisel3.experimental.{annotate, dedupGroup}
import chisel3.experimental.hierarchy.Definition
import chisel3.properties.Class
import circt.stage.ChiselStage
import firrtl.transforms.DedupGroupAnnotation
import chisel3.experimental.hierarchy._
import chisel3.util.circt.PlusArgsValue
Expand Down Expand Up @@ -121,13 +122,20 @@ class DedupSpec extends ChiselFlatSpec {
}) === 3)
}

it should "work natively for desiredNames" in {
it should "work natively for desiredNames with ChiselStage (the class)" in {
assert(countModules(compile {
val top = new SharedConstantValDedupTopDesiredName
top
}) === 3)
}

it should "work natively for desiredNames with ChiselStage$ (the object)" in {
assert(countModules(ChiselStage.emitSystemVerilog {
val top = new SharedConstantValDedupTopDesiredName
top
}) === 3)
}

it should "error on conflicting dedup groups" in {
a[Exception] should be thrownBy {
compile {
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