Enhanced Alignment Options for Verilog Formatter

[ButterSus]

This PR implements a new values for for the formatter:

   --named_parameter_alignment (Format named actual parameters:
      {align,flush-left,preserve,infer,align-both,align-both-separated,align-both-spaced}); default: align-both-spaced;
    --named_port_alignment (Format named port connections:
      {align,flush-left,preserve,infer,align-both,align-both-separated,align-both-spaced}); default: align-both-spaced;

It helps aligning closing parentheses. The new default is align-both-spaced (old one is align).
For more examples look here.

[linux-foundation-easycla]

• ✅login: ButterSus / (a7284ab)

The committers listed above are authorized under a signed CLA.

[hzeller]

Thanks for your contribution!

When you continue working on it, can you add a unit test to test the behavior of the new choice for alignment ?
Do you have heuristics that can implement the 'infer' behavior in this case as well ? E.g. if there is more than two spaces seen (e.g. .foo(foo )) it could infer that the user prefers this setting and applies it to the whole block.