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@enjoy-digital enjoy-digital released this 03 Oct 08:45
· 15 commits to master since this release
2025.08
05ddccb

[> 2025.08, released on October 3th 2025

[> Fixed

  • tools/json2dts : Fixed sdcard support in device tree generation (PR #2292, 29a8c3cdb).
  • software/litesdcard : Fixed warnings in litesdcard software (PR #2273).
  • cpu/ibex : Fixed missing add_sources calls (PR #2268).
  • tests/test_integration : Fixed file mode to allow reading logs on boot failure (PR #2264).
  • build/efinix : Fixed programmer compatibility and bitstream file copying, added CLKOUT_DYNPHASE_EN support (PR #2247).
  • tools/litex_json2dts_linux : Fixed USB OHCI DT naming (mac->usb) and L1 cache size reporting (PR #2251).
  • build/colognechip : Fixed DDR inversion issue (PR #2274).
  • tests/test_integration : Temporarily disabled coreblocks due to pipx issue (bc25ed7fd).
  • platforms/xilinx_zcu106 : Fixed user button pin according to user guide (PR #681).
  • targets/hyvision_pcie_opt01_revf : Fixed J9 pinout for correct board edge alignment (PR #682).
  • platforms/berkeleylab_marble : Removed IOSTANDARD from mgtrefclk pins to resolve Vivado warnings (3e77bc6).
  • litepcie/frontend/dma : Added FIFO resets to LitePCIeDMABuffering to prevent incorrect behavior (PR #148).
  • litesdcard/phy/SDPHYClocker : Fixed clock divider logic for div 0,1,2,3,4,5,8 cases (PR #40).
  • soc/cores/naxriscv : Fixed git submodule not being set to the right hash (PR #2332).
  • bios/isr : Removed warning for "no previous prototype for 'plic_init' [-Wmissing-prototypes]" (PR #2333).
  • tools/litex_json2dts_linux : Fixed clint addition to DTS by checking memory map instead of CPU type (PR #2335).
  • soc/interconnect/axi : Fixed AXIInterfaces initialization with correct id_width (PR #2320).
  • build/gowin/gowin.py : Fixed WSL issue with Gowin toolchain detection (PR #2308).
  • build/efinix : Fixed get_pad_name_xml for Topaz (PR #2297).
  • build/io/efinix : Fixed DDR Input timing (PR #2311).
  • build/altera/common : Fixed Agilex5SDRTristateImpl parameters and reset synchronizer (PR #2318).
  • soc/cores/ram/efinix_hyperram : Fixed clkout frequency and TristateImpl for TSTriple (PR #2295).
  • build/vivado : Fixed synth_ip warning by switching to non-project mode (PR #2294).
  • build/vhd2v_converter : Fixed mutable defaults in init (f8a1a213d).
  • soc/doc : Fixed CSR register calculation for little endian ordering (PR #2270).
  • build/[colognechip,gowin]/common : Fixed SDRInput parameters order in SDRTristateImpl (PR #2328).
  • soc/cores/clock/intel_agilex : Fixed clkin_name if signal type is ClockSignal (587b1b374).
  • bios/litedram : Fixed indexes of csr_rd_buf_uint8 (420591a1a).
  • litepcie/phy/xilinx_usp/m_axis_rc_adapt_512b : Fixed cq/rc typo (51da1ba).
  • litepcie/phy/s7pciephy : Added false path constraint on pclk_sel signal (44362da).
  • litei2c/phy : Fixed truncating complaint from toolchain (6fbef5b).
  • liteeth/phy/titanium_lvds_1000basex : Fixed regression on presented data to Decoder8b10bIdleChecker (fec700b).
  • platforms/berkeleylab_obsidian : Fixed configuration of SPI flash (PR #692).
  • platforms/colorlight_5a_75e : Fixed typo in connectors (PR #685).
  • targets/arrow_axe5000 : Fixed call to Agilex5PLL after litex core changes (PR #694).

[> Added

  • sim/verilator : Added state save and load functions for Verilator simulation (PR #2261).
  • build/xilinx/vivado : Added Device Image (pdi) generation support for Vivado builds (PR #2272).
  • software/bios/liteeth : Added ping command and BIOS support for responding to ping requests (PR #2287).
  • cores/cpu/vexiiriscv : Added architecture details in human-readable name (PR #2286).
  • tools/json2dts_zephyr : Added default IRQ priority of 1 for PLIC (PR #2285).
  • software/litesdcard : Added support for changing PHY modes (x1, x4, x8) (PR #2275).
  • soc/cores/prbs : Added errors_width parameter to improve timing in some designs (bc6a6f015).
  • software/bios/liteeth/udp : Added broadcast support (PR #2263).
  • tools/json2dts_zephyr : Updated interrupt naming for SPI flash core (PR #2271).
  • soc/cores/spi : Added interrupt support for LiteSPI and moved PHY to core for single CSR slot usage (2438c558e, befcbbc9b).
  • soc/cores/i2c : Added interrupt support for LiteI2C (3b4708db4).
  • tests/test_integration : Added ibex and vexiiriscv CPUs to boot tests (d170f08dd, e3b8bf653).
  • build/tools : Added _tail_file function and tail_log parameter to subprocess_call_filtered for colored build log output (f5e5514b3).
  • soc/integration : Exposed check_duplicate argument in add_ip_address_constants and add_mac_address_constants (PR #2259).
  • build/lattice/icestorm : Added support for pin pull-up configuration (PR #2256).
  • cores/usb_ohci : Added InterruptPin class for standard IRQ allocation (PR #2252).
  • tools/litex_json2dts_linux : Added local MAC address to ethernet device tree and L2 cache topology support (a3b36c125, 2781b0124).
  • cpu/naxriscv : Added support for generating cache sections in DTS (e1986d554).
  • soc/cores/clock : Added CologneChip GateMatePLL import (eda4e49b7).
  • litesdcard/phy : Added support for changing modes (x1, x4, x8) (PR #38).
  • liteiclink/serdes/gtp_7series : Added rx_prbs_errors_width parameter to add_prbs_control and add_controls (ef9c295).
  • litei2c/master : Added interrupt option (ad7ec63).
  • litepcie/gen : Added support for specifying DMA data_width in .yml configuration (2682042).
  • litepcie/frontend/ptm : Added named Time Clock Domain to avoid conflicts in larger designs (029a578).
  • soc/cores/cpu/zynq7000 : Added UART, SPI, I2C, and GPIO support with EMIO/PS configurations (PR #2340).
  • soc/cores/cpu/coreblocks : Added small_linux config and CoreSoCks wrapper support (PR #2339).
  • soc/cores/clock/intel_agilex : Added Altera Agilex PLL core (PR #2324).
  • build/altera/quartus : Added noprune attribute support and clock_constraints object (PR #2336).
  • build/lattice/trellis : Added argument to override bitstream's IDCODE (PR #2309).
  • build/altera/common : Added specials for Agilex DifferentialInput/Output and Tristate Implementation (PR #2318).
  • build/lattice : Added SDR tristate specialisation for ECP5 (PR #2326).
  • build/altera/quartus : Added selection between quartus_cpf and quartus_pfg for file conversion (PR #2318).
  • software/system : Added functions to clean/invalidate/flush cache (PR #2325).
  • soc/cores/cpu/vexiiriscv : Added cache management functions (PR #2325).
  • liteeth/mac/core : Allowed using core_dw smaller than phy_dw (PR #177).
  • liteeth/mac : Used one CRC engine for Checker (PR #183).
  • liteeth/phy/rmii : Added use of rx_er if it exists (PR #194).
  • liteeth/phy/titanium/trion rgmii : Added improvements and multibit IO support (PR #181).
  • litesdcard/phy : Added CSRs for timeout configuration (PR #43).
  • litespi/phy/sdr : Added extra_latency like in DDR phy (PR #89).
  • litespi/modules : Added MX25U25645G flash (PR #88).
  • litedram/modules : Added W989D6DBGX6 (PR #366).
  • litei2c/clkgen : Added scl_o/oe signals for code simplification and external access (166e2f6).
  • liteiclink/serdes/gtx_7series : Added rx_prbs_errors_width parameter (1cddcd4).
  • build/radiant : Added false paths to .pdc file generation (PR #2312).
  • build/efinix/clock/pll : Added nclkout argument to create_clkout (PR #2300).
  • Boards/targets : Added support for Machdyne Kolsch (PR #679).
  • Boards/targets : Added support for Alinx AX7203 with platform and target (PR #678).
  • Boards/targets : Added HDMI support for Alinx AX7203 (PR #680).
  • Boards/targets : Added USB option using PMOD connector JB for Digilent Nexys Video (2 USB-OHCI ports) (PR #672).
  • Boards/targets : Added SD card support for CologneChip GateMate EVB (PR #673).
  • Boards/targets : Added HyperRAM support for CologneChip GateMate EVB (PR #670).
  • Boards/targets : Added missing enable pin for 20 MHz VCXO on BerkeleyLab Marble (PR #676).
  • Boards/targets : Added support for Icepi Zero (PR #693).
  • Boards/targets : Added support for Berkeley Lab Obsidian A35 (PR #686).
  • Boards/targets : Added support for Efinix TZ170 J484 Dev Kit (PR #691).
  • Boards/targets : Added support for Arrow AXE5000 (Altera Agilex 5) (PR #689).
  • Boards/targets : Added support for ULX5M-GS (PR #688).
  • Boards/targets : Added support for QMTech Cyclone10 Starter Kit - 10CL080 (PR #683).

[> Changed

  • soc/litesdcard : Moved litesdcard modules to a parent class for add_sdcard(), renamed irq to ev (PR #2281, b46e06182).
  • software/litesdcard : Removed limitations for clock divider (PR #2276).
  • cpu/vexiiriscv : Updated recommended commit to latest dev (ee6c3102b).
  • build/efinix/efinity : Updated to use efx_run for builds, added tail_log parameter for log redirection, and set CLKOUT_DYNPHASE_EN (PR #2247, 83a14dd64).
  • build/colognechip : Removed forced ram_style=distributed (PR #2254).
  • ci/tooling : Updated to use GHDL from OSS CAD Suite and bumped to latest version (5e58ab1ba).
  • platforms/digilent_nexys_video : Added PMOD connectors (6bbca0e).
  • targets/berkeleylab_marble : Made max I2C interface optional (74cd48d).
  • platforms/berkeleylab_marble/marblemini : Removed redundant files (PR #675).
  • litesdcard/phy/SDPHYClocker : Reworked clock divider to use down-counter, simplified logic, and ensured frequency <= configured (PR #40).
  • litesdcard/phy : Set default data_width to 4x (PR #38).
  • soc/cores/cpu/coreblocks : Updated to 2025-09 with small_linux config and Vivado hacks (PR #2339).
  • soc/cores/clock/intel_agilex : Refactored PLL core and updated SDC constraints (PR #2336).
  • build/altera/platform : Refactored Agilex special overrides for Agilex 3 support (PR #2334).
  • soc/interconnect/axi : Optimized AXI bus with mode, split read/write, and faster read (PR #2289).
  • build/colognechip : Enabled multipliers with peppercorn toolchain (PR #2319).
  • soc/cores/uart : Switched to EventSourceLevel irq and exposed rx_fifo_rx_we (PR #2319).
  • soc/integration/csr : Improved read/write handling for big/little endian ordering (PR #2270).
  • soc/ethernet : Used phy_cd name directly from phy for multiple PHY support (PR #2163).
  • soc/litespi : Improved add_spi_flash with QPI activation, kwargs, and wait for quad mode (PR #2313).
  • build/io/Tristate : Added support for i/i1/i2 being None in SDR/DDR Tristate (PR #2310).
  • build/efinix/common : Updated to use add_iface_io (PR #2293).
  • build/xilinx/vivado : Switched to non-project mode and made verilog headers global (PR #2294).
  • soc/cores/ram/efinix_hyperram : Modernized PLL uses and exposed CTOR params (PR #2295).
  • build/efinix/clock/pll : Used margin for frequency check (PR #2299).
  • liteeth/mac/core : Added docstrings and allowed smaller core_dw (PR #177).
  • liteeth/mac/sram : Simplified logic and named memory (PR #191).
  • liteeth/phy/titanium_lvds_1000basex : Cleaned up and refactored for readability and reduced resources (PR #192).
  • litesdcard/phy : Made use of LiteXModule (PR #46).
  • litesdcard/crc16 : Moved CRC16 check to phy and reworked tests (PR #45).
  • litesdcard/core : Moved block delimiter into core (PR #44).
  • litespi/core/mmap : Excluded write code when disabled (PR #87).
  • litespi/phy : Added kwargs support (ef806bd).
  • litei2c/phy/clkgen : Made scl_o a Constant again and removed unused i from SDRTristate (8b6f5e8, c34fdb8).
  • ci/github_actions : Bumped actions/setup-python from 5 to 6 (PR #690).
  • ci/github_actions : Bumped actions/checkout from 4 to 5 (PR #687).
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