2026.04

[> 2026.04, released on May 26th 2026

[> Fixed

• litex/soc/software/liblitesdcard : Fixed SD card initialization by waiting for the card to become ready (PR #2420).
• litex/soc/cores/cpu/neorv32 : Fixed NEORV32 source lists, wrapper interrupt port naming, and VHD2V simulation conversion path (a266e47e3, 68b659976, 5f12f510e).
• litex/soc/cores/cpu/gowin_emcu : Fixed EMCU IO-region exposure to the AHB2 Master extension and documented the separate APB2 extension windows (PR #2461, c4f606aa2).
• litex/soc/cores/clock/xilinx_common : Fixed 7-Series MMCM fractional divide handling and restored highest suitable VCO frequency selection (2fdfa356d, 9ab47cc52, e9324462a).
• litex/soc/cores/clock/xilinx_usp : Fixed/documented UltraScale+ simulation primitive handling and restored the conservative SIM_DEVICE selection after build regressions (PR #2456, a4658cfd9, 56b55d7dd, 4065f0bb4).
• litex/soc/cores/clock : Fixed Lattice oscillator range limits, tightened PLL API/frequency/phase validation, tolerated Efinix floating-point noise, remapped sparse Efinix feedback outputs, and improved error diagnostics (d949e1650, 54f613c63, 97ad6b57a, fbe507c89, 30e8b86e3, d49e4d026, 0ae3d6749, c7a2bd71b, a783810b6, 9a1f7745d).
• litex/soc/cores/gpio : Fixed GPIOTristate sharing by exposing LiteX-style o, oe, and i intermediate signals for user logic and platform lowering (PR #2458, 04ebd7421).
• litex/soc/cores/jtag : Fixed ECP5 JTAG PHY TDO timing, RX ready persistence, and JTAGUART robustness for background operation (PR #2411, PR #2410, 5837a7d1e).
• litex/build/xilinx/vivado : Fixed timing report typo, aligned CDC timing constraints with Migen-generated structures, and narrowed emitted asynchronous clock groups to relevant clock objects (4452113fa, eaf58d953, e0be1da6e).
• litex/build/microsemi/platform : Disabled register initialization in ProASIC3 Verilog generation (unsupported by the device/tool flow) (a274bc74b).
• litex/build/efinix : Fixed Efinity 2025.2 builds, applied default tool parameters consistently, preserved Verilog library information in project data, restored design-file library helper compatibility, detected the toolchain from PATH, and defaulted Verilog sources to the default library (PR #2438, b0622815b, 8982a6a01, 761f62ca0, d8ea103d9, 56b134056).
• litex/build/io / vendor platforms : Fixed IO primitive width/override validation, scalar compatibility aliases, DDR async-input preservation, and per-bit/vendor lowering across generic, Xilinx, Gowin, Efinix, and Lattice paths (74f37cbae, 1c956bbf9, 46bc89e77, 6d39206db, cff44200a, beecfc1c8, 85891a8c7).
• litex/soc/interconnect/wishbone / avalon : Fixed burst upconversion and registered burst read handling, with continuous burst and latency regression coverage (PR #2436).
• litex/soc/interconnect/axi / integration : Fixed AXIDownConverter FIXED burst handling and replaced AXI-to-Wishbone/AXI-Lite SRAM fallbacks with native AXI paths, with expanded burst/width regression coverage (94f662d07, 2fae162d0, e8bac9bba).
• litex/soc/interconnect/axi / dma : Fixed AXI up-converter lane writes and aligned Wishbone DMA bursting with the bus capabilities (1a290a20b, 6b5216421).
• litex/tools/litex_term : Fixed serial upload CPU overload by waiting for acknowledgements instead of busy polling (PR #2450).
• litex/tools/litex_term : Fixed crossover UART remote-server port forwarding and base-address parsing while preserving constructor compatibility (PR #2459, ac8831617).
• litex/soc/software/bios / tools/litex_term : Fixed serialboot recovery from malformed or timed-out frames, added robust upload abort handling, and restored conservative upload calibration/pacing for USB-ACM links (PR #2452).
• litex/soc/software/bios : Fixed and hardened boot JSON parsing, including malformed-token handling, JSON token helper availability when Ethernet support is disabled, and guarded helper compilation to avoid unused-function warnings in builds without JSON boot backends (97f23539f, PR #2453, dab2e1341).
• litex/soc/software/bios / libliteeth : Hardened console input, dynamic Ethernet address parsing, TFTP/serialboot load bounds, boot-image range validation, manifest error reporting, memory dumps, and UDP packet-length checks (3f63c2e57, caa4eb684, 5b855be2b, d47d4b3e3, e53d98738, cfb459fa4, 1a3d8b54a, 292aad467, b330413c1).
• litex/soc/software/liblitedram : Fixed BIST build compatibility with recent GCC versions (PR #2460, 6cb62f13e).
• litex/soc/software/liblitedram : Fixed/accelerated GW5 DDR calibration flow with faster tap search, stronger fast-write-leveling checks, burst-detection validation, and post-update DQS buffer resync (5ee84dfa8, c487019a6, 9ee9fb072, 5af41cab2, 611f22b35).
• litex/gen/sim/vcd / build/sim/verilator : Fixed simulator failure reporting by preserving Verilator run failures and using the correct temporary VCD path for local outputs (0d76a09d5, 9434cd74c).
• litex/gen/fhdl/verilog : Fixed hierarchical tristate and memory ownership in generated Verilog (7d302fcb, a7a9d1c7d).
• litex/soc/integration/soc / export : Fixed generated export edge cases, bus-handler rollback on failed additions, and AXI-to-AXI-Lite bus adaptation (8efa3afa8, 329559c72, 47d30a0ad).
• litex/build / tools / remote : Fixed tool/programmer error propagation, OpenOCD verify command formatting, LiteXTerm image validation under optimized Python, platform import error reporting, and PCIe BAR descriptor handling (25022e301).
• litex/tools/remote : Fixed shared helper defaults, remote-client CSR-width initialization, timeout handling, PCIe server-info base translation, Etherbone burst chunking, read-merger edge cases, and CLI memory-transfer cleanup while adding focused regression coverage (a37375e8b, 76ffc6b6d, 29f0aed44, 59e8c5e88, 5fad2627d, 3c0e156ab).
• litepcie/tlp/packetizer : Fixed 128-bit 4DW payload handling by keeping the payload beat in the DATA state (00e5bcfe).
• litepcie/software/kernel / liteuart : Fixed coherent DMA-buffer mmap handling and improved LiteUART RX/TX polling robustness (c52a6fe, e5f4760).
• litepcie/phy/gowin / phy/lattice : Fixed Gowin requester identity, MSI vector mapping, and lane swapping; fixed LFCPNX requester-ID handling, RX TLP boundary preservation, PCIe user clock/reset usage, DMA sizing, MSI-X interrupt support, and LMMI requester-ID fixup (33efe92, 90e2634, 4d5f5b0, a0655ca, 63f1cc4, c787773, df33d56, 736d4ff, 07531c5).
• liteeth/phy/1000basex : Fixed PCS timer scaling and expanded coverage for CDC clocks, gearbox ordering, and LSB-first datapaths (d341f370, 58304bdd, f571f951, 7cbe6e99, 7ccdb530, e81851cc, 804955c2).
• liteeth/core/ptp / igmp : Hardened PTP/IGMP handling around multicast delay requests, TSU fractional initialization, link-gated reports/joins, datapath width matching, final-byte marking, and counter cleanup (89317174, 4f4285a8, ca1e75ed, 39199eb4, fc56e93c, 10ea52e9, 2e1060ca, e61e7881, c40cfbbb).
• litedram/gen : Fixed import of get_sdram_phy_settings after upstream model changes (PR #375).
• litedram/modules : Fixed standalone generator command-latency handling and added ISSI SDRAM modules (PR #378, PR #379, PR #368).
• litedram/phy/gw5ddrphy : Aligned GW5 DDR PHY control latencies with the GW2 DDR PHY (c7bcb5d).
• liteiclink/serwb/phy : Fixed PLL reset deglitching and brute-force clock aligner CDC capture domain handling (PR #28, PR #27).
• litesdcard/phy : Fixed command-done flag handling after command responses (PR #54).
• litespi/phy/generic_sdr : Fixed SDR no_read, SPI mode reset/default handling, and clock-generator start/reset corner cases (PR #96, PR #97).
• litescope/software/dump : Fixed invalid escape sequence warnings in dump regex handling (PR #51).
• litescope/test : Fixed LiteScope UART simulation waits to notice simulator exits cleanly (bc74bc4).
• targets/platforms : Fixed Ethernet support on MNT RKX7, Hyvision PCIe speedgrade handling, Tang Mega 138K PMOD naming, Tang Nano 9K HyperBus fallback behavior, and several target parser/configuration typos (PR #724, PR #732, 448f9d58, bb16fd91, 976dccfb).
• Boards/platforms : Fixed additional board-resource and programmer issues across Tang Console/Mega DDR, Hackaday Badge, Spartan-6 iMPACT, Bochen Jingxin, Mozart MX, XTRX, Time Card/Kintex BSCAN, Trenz flash programming, ULX4M CM4, and other platform definitions (034c5db2, b1baa138, 92cc0296, 4af612b7, 7a1b5860, 1f8bd6bb, 0770b5f3, df5f3c16, a4f73d11, ae316654).

[> Added

• litex/gen/fhdl/verilog : Added hierarchical Verilog generation support, including shared-module hierarchy handling and Verilator hierarchical build support (PR #2422).
• litex/build/amaranth2v / soc/cores/cpu : Added/introduced the Amaranth-to-Verilog converter flow and switched Minerva/Sentinel/Coreblocks to it with compatibility fallback where needed (PR #2409, 891eb2954, 210d2aaab).
• litex/soc/cores/cpu/fazyrv : Added RISC-V compressed instruction support (PR #2447).
• litex/soc/cores/cpu/coreblocks : Added Coreblocks PLIC support and refreshed the Coreblocks elaboration/packaging integration (5b2eaaecd, 100c044f6).
• litex/soc/cores/usb / luna_cdc_acm : Added the LUNA CDC ACM USB-UART wrapper, switched usb_acm integration to the LUNA backend, and extended it with external ULPI PHY support, target pad overrides in add_uart, and configurable direct/inverted ULPI clock handling (PR #2418, PR #2432, PR #2433).
• litex/soc/integration/soc / add_pcie : Added DMA buffering and MSI mapping controls to PCIe integration (5ad43630a).
• litex/soc/cores/dma : Added optional Wishbone burst tagging support for DMA interfaces (52e09d8ff).
• litex/soc/integration/builder : Added integrated_rom_auto_size / --no-integrated-rom-auto-size control to keep the requested integrated ROM size and pad BIOS contents deterministically (fe4c87a7d).
• litex/soc/integration/builder / build/log : Added default live litex.log generation under the builder output directory, with stdout/stderr/Python logging capture, early SoC log preservation, --build-log / --no-build-log controls, and ANSI-free log files while keeping colored console output (b815e651a, bc629791b).
• litex/build/xilinx/vivado : Added helper support for name-based false paths and generated clock constraints (9fe287f26).
• litex/build/colognechip : Added Peppercorn A2/A4 die/clocking controls and switched Peppercorn to the default CologneChip toolchain flow (PR #2444).
• litex/tools/litex_json2dts_zephyr : Added UART handler generation support (PR #2448).
• litex/tools/litex_json2dts_zephyr : Added dma-coherent DeviceTree property generation from CSR JSON metadata (PR #2455).
• litex/soc/cores/clock : Added consistent name support across direct-instantiation clock cores (Xilinx, Lattice, Gowin, GateMate/NX) to control generated primitive instance names (4cd599dae).
• litex/soc/cores/flash : Added initial BPI flash core support (PR #2414).
• litex/soc/cores/led : Added SK2812RGBW serial LED support and shared serial LED infrastructure with parameter validation (PR #2454, cfa86fa02, e52eb60c1).
• litex/soc/cores/jtag : Added ECP5JTAGPHY with Verilog shift register and AsyncFIFO CDC (PR #2411).
• litex/soc/cores/ram : Added USPHBM2 channel helpers for pseudochannel integration (011e7c40b).
• litex/soc/integration/soc : Added CSR address helper support for bus masters (7549f4e7e).
• litex/soc/software / software/libc : Added a minimal libc mode, including float-format support and reduced Meson probing for lightweight picolibc-based builds (PR #2425, 13ffc6be8, ab01e78a2, 316fe0141).
• litex/test : Added broader unit coverage for AXI, Wishbone, CSR, stream, UART, GPIO, video, PWM, DMA, watchdog, frequency-meter, FT245, DShot/ESC, and integration helpers (85761f161, f942aab5f, 86435f3d5, f813e9c12).
• litex/ci : Added Rocket Linux generation and ECPIX-5 smoke tests (9f9776bf1, 224ff287a).
• litex_release.py / doc : Added a dedicated release helper and process documentation with repository listing, tag validation, dry-run/preflight checks, phase resume/cwd-safe bump handling, release state recording, and temporary Git repository regression tests (9fac358ca, 79b91a108, b50836542, 6e339715a, afa9b7e36).
• packaging / release : Added PyPI publishing workflows and metadata support across LiteX, LitePCIe, LiteEth, LiteDRAM, LiteScope, LiteSPI, LiteSDCard, LiteICLink, LiteSATA, LiteJESD204B, LiteI2C, and LiteX-Boards (714f89031, 95f4731, cd479a4, 28521d8, 3f46493, 013d90b, 4630ba2, 878b9ef, 5ada696, 193f4d8, 15c7aaa, 25bfc3c3).
• doc/coding_style.md : Added LiteX coding style guide and examples for Python/gateware/test changes, plus command-line help text guidance (1b78f5228, ac8831617).
• litepcie/core / phy : Added initial Root Port support, TLP configuration transactions, and PCIe Gen2 support on Ultrascale/Ultrascale+ PHYs (0227789, 5a5ede7, 2d92c7d, 2f5097e, 6417252).
• litepcie/software : Added PCIe rescan tooling and shared DMA device file-descriptor support for user software (43a21eb, b5c8f01).
• litepcie/tlp : Added 32-bit datapath support (PR #163).
• litepcie/phy : Added direct pclk mux MMCM option for Xilinx PCIe PHY clocking (8312ab0).
• litepcie/phy/s7pciephy : Added helper support for 7-Series GT lane LOC constraints, optional PERST refclk gating, and MMCM/device speedgrade exposure (04105f6, a9357e9, 9e5ed80).
• liteiclink/serwb/phy : Added Spartan-7 support to the Xilinx 7-Series SERWB PHY (PR #30).
• litescope/software/driver/analyzer : Added polling delay handling to wait_done for more reliable analyzer completion (PR #48).
• litescope/core / software / test : Added optional LiteScopeAnalyzer RLE capture support with final-run flushing, driver/CLI controls, decoded sample limiting, and Verilator litex_sim UART end-to-end plus randomized/compatibility coverage.
• liteeth/core/ptp / igmp / bench : Added an IEEE 1588v2 Layer-3 PTP slave core, an IGMP multicast group joiner, and Arty A7 PTP bench/test utilities (PR #199).
• liteeth/phy : Added Agilex 3/5 RGMII PHY support and USRGMII IO delay configuration controls (PR #202, PR #201).
• litespi/modules : Added W25Q128JW flash support (PR #98).
• Boards/targets : Added Ethernet/Etherbone support for Alibaba XCKU3P, extended Microphase A7 Lite peripherals/variants, added initial YPCB board support, added HDMI output on Digilent Genesys2, added USB-ACM support on LambdaConcept ECPIX-5, added PTP support to Efinix TI375 C529 Dev Kit and Acorn Baseboard Mini, and extended configurable PCIe lane support across Xilinx targets, including PCIe Gen3 x8 on Alibaba XCKU3P and configurable lanes on additional Ultrascale+ boards (PR #724, 6b23f9fb, PR #722, PR #728, PR #731, 371333e9, 391c5c22, 30504c1d, 87410340, 4e47f7ea).
• Boards/targets : Added initial Terasic Atum A3-Nano (Agilex 3) board support with SDRAM, Ethernet/Etherbone, HDMI/DVI, SDCard/SPI-SDCard, and OpenFPGALoader/USB-Blaster programming support (PR #733).
• Boards/targets : Added accelerator shell support and switched related targets to LiteX USPHBM2 channel helpers (b746eced, f2660cd2, 91d26439, cac91bbd).
• Boards/platforms : Added and expanded board resources/connectors across Xilinx, Lattice, Digilent, Trenz, MicroFPGA, Microsemi, Alchitry, Numato, Efinix, Sipeed, NetFPGA-SUME, PlutoSDR, and related platform families (3dc608a8, 8f98cf7d, 2c89c208, 4c6d672e, e6eb331a, 3b6ec4b7, 1b4cb9cd, 7a27e973, 687f868d, 43c03b46).
• Boards/test / ci : Added board consistency guardrails, Etherbone static-IP checks, target inventory test-status reporting, and smoke coverage for excluded/no-compile/simple platform builds (4f7efa16, d501a2b3, 79c80adc, 77fd7177, 70882d44, 4645e585, e0fe1803, df889e8b, 467110d3, 075b2402, 1353d875).

[> Changed

• litex/build/converters / build/vhd2v : Harmonized converter APIs, normalized aliases/ports/domains/sources handling, stabilized generated file writes, and added compatibility coverage between old/new argument styles (PR #2409, 645157397, 687199df9, 90a4bcef1).
• litex/soc/cores/cpu : Refreshed CPU integration by avoiding hard Amaranth import failures during CPU discovery, switching NaxRiscv setup to the default branch, updating the recommended NaxRiscv/VexiiRiscv revisions, and cleaning up VexiiRiscv integration/config handling (PR #2404, PR #2403, PR #2449, 1b4f8629f).
• litex/software/bios / cpu/cva6 : Switched CVA6 cache flush handling to fence.i (c18922e6c).
• litex/soc/interconnect/stream / packet / test : Reworked stream/packet control-path corner cases under backpressure, clarified converter flow, added header encode/decode shift support, and substantially expanded regression coverage for FIFOs, CDC, width converters, routing, and packet boundaries (07b162232, 23facc547, 155efbe8a, 4308d76e7, 35ce65607, e49184d48).
• litex/soc/interconnect / cores : Reworked user-facing API validation from assert-only checks to explicit exceptions and tightened deprecated argument handling across bus interfaces, GPIO/I2S/UART, DMA/DNA/ICAP, HyperRAM, SPI, BlackParrot, and related helpers (3a13b4126, 19d3a3566, d0294db0c, 0f7105aa7).
• litex/soc/cores/clock : Reworked PLL candidate selection and clock input/output wiring helpers to prefer closest configurations and share named clock-output handling across vendor PLLs (e7856901f, bff3c6776, a3aa436bf, c19e0f507, a828694d7, 82a2ab677, 5342fa922, ace479841, 8a0d4b5c9).
• litex/soc/cores/ram / hyperbus : Reworked vendor RAM helper selection and hardened FIFO_SYNC_MACRO, Lattice RAM, Efinix HyperRAM, HyperBus timing, initialization-word, and wrapper validation with expanded simulation coverage (15ace7cb, 592d7458, 423bab25, 72c6c559, ae729f46, de49e104, 691479d5, fb8308f4).
• litex/soc/integration/soc : Reworked SoC integration compatibility/error handling, region defaults, DMA-bus sizing, SATA clock requirements, and CSR bridge naming around newer byte-addressed/AXI paths (4350536ce, d9cee7235, ab21eddf0, 6e7c4af92, a4f25351a).
• litex/soc/integration / builder / export : Further hardened builder/SoC validation, JSON import/export handling, generated software exports, memory image parsing, build-name/CPU reset handling, interrupt and SoC region validation, and optional build paths (1347fb0b0, aaf194e4f, 195a47df4, 4033dff44, 15923917a, e85638531).
• litex/soc/integration/soc : Further tightened SoC finalization and helper validation with instance-local maps, reproducible build timestamps, CPU/bus/CSR/memory-origin checks, dependency guards, clearer argument errors, and exact IO-region overlap checks (d8ec4b756, 77d05404d, 9c1750837, 90cd3df9a, fd3dec391, 7ddf39fe6, 66454b5b2, dded2e955, 119588348, 510193acf, 5f0d4a1ab).
• litex/build/parser : Forwarded parser kwargs to argparse for better LiteXArgumentParser compatibility (68822d137).
• litex/build/generic_platform/toolchain : Hardened generic platform/toolchain cleanup, caller cwd restoration, connector/resource handling, period-constraint diagnostics, explicit parser argument handling, and log-level validation (83fd540de, f27751140, 6107c55d).
• litex_setup.py / litex_repos.py : Reworked setup repository metadata into a shared litex_repos.py, kept standalone litex_setup.py auto-update/install flows working, hardened Git/pip/toolchain command execution and failure reporting, added dirty-tree update confirmation and clean expected exits, fixed repository tag fallback handling, added install-time repository preflight checks, and made --freeze emit reusable repository definitions (7430a850e, a859ce1da, 37c57020d, 391e49c7b, 786e984da, 76064094b, ae43af472, 5e4a4136c, ad23dae51).
• litex_setup.py / litex_repos.py : Reworked editable/local repository installs for PEP 517 and externally managed Python environments, disabled build isolation for local repos, and restored recursive VexRiscv-SMP clone handling (2a3ef9680, dc5fc1076, f507511a9, cdf48cb5d, 3214920a7, 0b1567556, 4b67db328).
• litex/build/gowin : Added Gowin toolchain support on macOS by adapting bundled-library selection from the gw_sh path (PR #2445).
• litex/ci : Reworked CI around cached Verilator/OSS CAD Suite/GCC toolchains and sharded pytest-split execution for faster, balanced integration coverage (65c3d435b, 1376b10ca, 4f7293af1).
• litex/soc/cores/video : Extended VideoTerminal control-sequence/color handling and added regression coverage for video terminal, timing generator, generic PHY, color bars, and TMDS encoder paths (9bf021f7a, 08f9c7589, ea1957a77, f813e9c12).
• litex/tools/litex_client/server/sim : Hardened simulator/server argument validation, server lock cleanup, GUI GPIO-count discovery and XADC updates, and remote/tool exception handling (fb750462, 6f634cb1, 5029ed03, 48d6319f, 71c38b01, 4228f769).
• litex/tools/litex_server / remote/comm_uart : Improved remote access throughput by replacing server lock polling with threading.Lock, caching server-side read capabilities, batching UARTBone readback, and selecting larger baudrate-aware UARTBone write bursts with a conservative timeout margin (2bd6295e8, fb5887ad7).
• litex/software/libc / software : Updated picolibc 1.8 integration by refreshing makefiles and Meson overlays, fixing build paths, restoring missing stdlib sources/includes, and honoring native libc toolchain selections (PR #2424, c4e4554cb, 00639b68d, 142204158, 32fc68dc3, 389204929, 857b8ae51).
• litex/soc/software/liblitedram : Documented SDRAM initialization/calibration flow and refreshed calibration handling around fast-write leveling and GW5 DDR updates (79d3d446b, c4bbc74d4, 5ee84dfa8, c487019a6, 9ee9fb072).
• litepcie/phy/xilinx : Reworked Xilinx PCIe PHY support around unified LiteX-native AXIS adapters across 128/256/512-bit widths, direct PHY mappings with preserved CQ/RC tuser metadata, removed legacy adapter wrappers, and added broader adapter property/backpressure coverage plus Verilator linting (07d16f6, 0a26ee8, 0e24657, 22113a8, c9cb021, 0a00eac).
• litepcie/frontend/dma / tlp / test : Reworked DMA progress/status reporting, rounded descriptor lengths to bus words, buffered raw requests before arbitration, improved DMA writer/status timing, and refactored TLP header inserter/extracter paths into generic engines with dedicated unit tests (aad9c39, 6740ec5, 3a76272, 3c0e4b9, 216515d, 981164c, PR #154).
• liteeth/mac / frontend/stream / core : Added configurable MTU/jumbo-frame support, fixed Stream2UDPTX freeze/truncation on mid-packet disable, and made UDP port CDC depth configurable (PR #197, 25a4eb6).
• litedram/frontend : Reworked narrow Wishbone burst coalescing and CSR registration for current LiteX integration (916b8b6, 744b143).
• liteiclink/serdes / serwb : Harmonized SERDES initialization helpers, transceiver wrapper controls, and SERWB wrapper style (aa9181f, 5beb6a7, 619cdef).
• liteiclink/serwb/kuserdes : Completed UltraScale+ primitive support in KUSERDES and added bitslip handling (2fd582a, 816996a).
• litesata/packaging : Cleaned packaging and test references for the current release flow (2998b8d).
• litespi/phy/generic_sdr / core : Reworked SDR clock divider generation, chip-select timing, and per-core divider selection for better SDR/DDR compatibility (PR #95).
• Boards/targets / ci : Continued the migration to LiteXArgumentParser, standardized target option/help formatting and Ethernet/UART argument behavior, normalized active-low target signal naming, added parser-style CI checks, and updated USB-UART capable boards to the LUNA ACM backend where applicable (PR #727, PR #726, b02aa763, 5d3bf914, 453b125c).
• Boards/platforms / prog : Switched Alibaba XCKU3P and Kosagi Netv2 programmer flows to include OpenFPGALoader support, modernized OpenOCD config syntax, shipped prog/*.cfg files in installs, and reused the new LitePCIe 7-Series GT LOC helper on affected targets (PR #724, 505e1ee2, a67e8096, 036a6e5f).
• Boards/targets : Updated Gowin/TD bitstream extension handling, added DeckLink Quad HDMI Recorder PCIe reset wiring, switched SQRL FK33 to add_pcie, and cleaned platform/target formatting and imports (765e9b88, PR #734, 3c6dbff5, 0d2cdd69).