Test bumping Ubuntu version - #8
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SonicField
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Feb 18, 2026
Save JIT return address to [SP, #8] before each BL/BLR instruction, and read it back in getIP() at frame_base - frame_size - kPointerSize. Falls back to saved LR at [FP+8] when slot reads zero (no call yet). Root causes fixed: 1. Double-counting: old FP-relative STR offset added kPointerSize on top of stack_frame_size which already includes kStackAlign, writing below SP. 2. Register clobbering: translateCall isReg case could have call target in x12/x13 which saveReturnAddress overwrote. Now moves target to x16 first. 3. ptr_resolve scratch: large frame offsets triggered ptr_resolve paths using x13 as scratch, clobbering the call target. SP-relative [SP,#8] uses simple immediate addressing with no scratch register. Validated: 15/15 CPU modules pass (default + PYTHONJITLISTALL=1), 8/8 GPU modules pass with zero regressions, GPU JIT smoke test pass (add/matmul/relu on NVIDIA GB200).
SonicField
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Feb 18, 2026
… overlap) Store the saved-IP at [FP + saved_ip_fp_offset] instead of [SP, #8] to eliminate the theoretical overlap between the saved-IP slot and vectorcall args[0] at kVectorcallArgsOffset (also [SP+8]). Key change: pre-compute saved_ip_fp_offset in getVectorcallEntry after register allocation but before generateCode, because generateAssemblyBody (which emits ADR+STR for saved-IP) runs before computeFrameInfo. A JIT_CHECK in computeFrameInfo verifies the pre-computed value matches. Files changed: environ.h - add saved_ip_fp_offset field to Environ gen_asm.cpp - early offset computation + JIT_CHECK assertion gen_asm_utils.cpp - emitCall uses FP-relative ptr_resolve autogen.cpp - translateCall uses FP-relative ptr_resolve code_runtime.h/cpp - savedIpFpOffset accessor for CodeRuntime frame.cpp - getIP reads from FP + savedIpFpOffset frame_shadow.cpp - shadow frame getIP uses same offset Test results (15/15 CPU, PYTHONJITCOMPILATIONTHRESHOLD=1000): 11 PASS, 4 FAIL (all pre-existing, verified with CINDERJIT_DISABLE=1)
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Aug 10, 2026
Summary: Adds `kLoadPair`, the load-side counterpart to the existing `kStorePair`, so adjacent 64-bit loads can be emitted as a single `ldp`. It takes the same (offset, base) shape as `kStorePair`, with the first destination as the output and the second as an extra input. On x86 it lowers to two `mov`s. The first user is `PopulateEntryBlock`, which loads the vectorcall arguments from consecutive slots of the argument array on every JIT function entry: ``` mov x10, x1 mov x10, x1 ldr x1, [x10] ldp x1, x2, [x10] ldr x2, [x10, #8] -> ldp x3, x4, [x10, #0x10] ldr x3, [x10, #0x10] ldp x5, x6, [x10, #0x20] ldr x4, [x10, #0x18] ldr x5, [x10, #0x20] ldr x6, [x10, #0x28] ``` One important caveat about this - we have no support for instructions w/ multiple outputs. So this instruction is only available after register allocation where we've previously allocated the output register as part of a load instruction. The current usage runs after register allocation and the next diff adds a post-alloc pass as well. Pairing is limited to aarch64 so x86 output is unchanged. Reviewed By: alexmalyshev Differential Revision: D114969843 fbshipit-source-id: 6f77f125a67b19201aac2d52dbcace9fc8bc3837
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Aug 18, 2026
Summary: Take 2 of D114969843. This gets the same treatment as D116050156 so we use an address adjustment + load pair instead of two ldr's. Adds `kLoadPair`, the load-side counterpart to the existing `kStorePair`, so adjacent 64-bit loads can be emitted as a single `ldp`. It takes the same (offset, base) shape as `kStorePair`, with the first destination as the output and the second as an extra input. On x86 it lowers to two `mov`s. The first user is `PopulateEntryBlock`, which loads the vectorcall arguments from consecutive slots of the argument array on every JIT function entry: ``` mov x10, x1 mov x10, x1 ldr x1, [x10] ldp x1, x2, [x10] ldr x2, [x10, #8] -> ldp x3, x4, [x10, #0x10] ldr x3, [x10, #0x10] ldp x5, x6, [x10, #0x20] ldr x4, [x10, #0x18] ldr x5, [x10, #0x20] ldr x6, [x10, #0x28] ``` One important caveat about this - we have no support for instructions w/ multiple outputs. So this instruction is only available after register allocation where we've previously allocated the output register as part of a load instruction. The current usage runs after register allocation and the next diff adds a post-alloc pass as well. Pairing is limited to aarch64 so x86 output is unchanged. Reviewed By: yoney, alexmalyshev Differential Revision: D116050157 fbshipit-source-id: d6102c84812d46a0fc5495b0b6a7064fcc4a24a8
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