Importing VQM to Quartus

Original tetris project includes PLL, tristate IOs and a decent ammount of RTL logic.

Because of limited support for primitives like PLLs and tristate IOs, we choose to synthesize only RTL logic with Yosys, and then import resulting "partial" VQM netlist into Quartus project, and complement all lacking parts there.

The problem is that all netlist ports get IO buffers, assuming that it will connect directly to FPGA pins. We asked how to tell Yosys not to instantiate IO buffers? in Yosys community and got positive reaction on that:

I've now added an option for this in commit b4c1d30. Now you can disable inference of IO buffers with synth_intel -noiopads

After that, we can simply include Yosys-generated VQM netlist in latest Quartus as an ordinary project source file and connect it with other project modules. Example below shows RTL view of project, that includes PLL and this Yosys-generated VQM netlist.