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Konstantin edited this page May 12, 2018 · 1 revision

Verilog Quartus Mapping File (.vqm) is an output netlist file that you got after successfull synth_intel command run.

Information from old Altera help documentation:

An ASCII text file (with the the extension .vqm) that is generated either by using the Synplicity Synplify software or by the Quartus® II software when you turn on Incremental Synthesis in the Synthesis page in the Settings dialog box (Assignments menu), and then compile the design. A VQM File is an atom-based Verilog HDL netlist file that defines all logic for a Synplify design or for a particular compilation focus when used as a part of an incremental compilation, using a subset of Verilog HDL constructs.

When generated from an incremental compilation in the Quartus II software, the VQM File is placed in the \atom_netlists\ directory. You can then use the VQM File by creating and then compiling a new project for the file. You can use the Synplicity Synplify software to convert a VHDL or Verilog HDL design file created with the Synplicity Synplify software to a VQM File that can be processed using the Quartus II Compiler. Altera® recommends that you do not edit the VQM File directly.

Current support for VQM

See https://www.altera.com/support/support-resources/knowledge-base/solutions/rd07312007_434.html

Short quotes from that document:

  • "VQM-generation capability is available only for backwards-compatibility for older device families"
  • "Note that VQM files generated by third-party synthesis tools work correctly"
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