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Initial analisys
Konstantin edited this page May 12, 2018
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yafpgatetris project, which we take as a starting point, has following features:
- written mostly in SystemVerilog
- supposed for DE1-SoC development board in Quartus IDE
- includes 125MHz PLL IP-core
- code extensively uses SystemVerilog features like enums, typedefs
- game data is mostly stored in multi-dimentional packed arrays, which is also a SystemVerilog-only feature
Many SystemVerilog features have no or limited support in Yosys. Hardware primitives like PLLs, tristate IO buffers are not supported. Supported multi-dimentional memory type is very restrictive compared to packed arrays:
- https://github.com/YosysHQ/yosys/issues/248
- https://www.reddit.com/r/yosys/comments/2cq8ip/multidimensional_arrays_in_verilog/
- https://www.reddit.com/r/yosys/comments/44d7v6/arrays_as_inputs_to_modules/
All that mentioned problems is a challenge for us in this project. We will modify and adapt yafpgatetris code to make friendly to current version of Yosys framework