Fix EJTAG UART plain Verilog lint compatibility

[lcapossio]

Summary

• Move EJTAG UART baud-check scratch declarations out of an unnamed procedural block so the RTL parses as plain Verilog.
• Change the RTL lint pass from iverilog -g2012 to iverilog -g2001 so CI catches SystemVerilog-only constructs in .v files.

Validation

• python tools\sync_version.py --check
• ruff check .
• fcapz --help
• python sim\run_sim.py --lint-only
• python sim\run_sim.py
• python -m pytest tests\ -v --tb=short
• wsl -e bash -lc "cd /mnt/c/Projects/fpgacapZero && python3 sim/run_verilator_lint.py --self-test"

Verilator lint passed for 37 RTL targets and confirmed the intentional MULTIDRIVEN self-test.