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Issues list

[HW][SV] Transition "HWToSV" to "ProceduralCoreToSV" pass. HW Involving the `hw` dialect Verilog/SystemVerilog Involving a Verilog dialect
#7335 opened Jul 17, 2024 by fzi-hielscher Loading…
8
[SV] Combine RegOp/LogicOp -> sv.var enhancement New feature or request Verilog/SystemVerilog Involving a Verilog dialect
#6318 opened Oct 19, 2023 by dtzSiFive
3
[SV] Incorrect inlining of continous assignment to"logic" variable (LogicOp) bug Something isn't working Verilog/SystemVerilog Involving a Verilog dialect
#6317 opened Oct 19, 2023 by dtzSiFive
[SV] Introduce SystemVerilog string type Verilog/SystemVerilog Involving a Verilog dialect
#5640 opened Jul 20, 2023 by mortbopet
3
[SV] Rename SV passes to reflect that they're SV passes and not HW HW Involving the `hw` dialect Verilog/SystemVerilog Involving a Verilog dialect
#5581 opened Jul 13, 2023 by mortbopet
[SV] SCF to SV lowering Verilog/SystemVerilog Involving a Verilog dialect
#5578 opened Jul 12, 2023 by teqdruid
[SV] Crash in P/BPAssignOp verifiers for hw.inout ports bug Something isn't working good first issue Good for newcomers Verilog/SystemVerilog Involving a Verilog dialect
#5566 opened Jul 12, 2023 by mortbopet
[SV] Replace assert/assume/cover with Verif dialect ops Verilog/SystemVerilog Involving a Verilog dialect
#5285 opened May 26, 2023 by fabianschuiki
1
[SVExtractTestCode] Behavior w/ and w/o Dedup Verilog/SystemVerilog Involving a Verilog dialect
#4229 opened Nov 2, 2022 by seldridge
[SV] Generic SVAttributes Verilog/SystemVerilog Involving a Verilog dialect
#3430 opened Jun 28, 2022 by uenoku
9
[SV] Generate case/if blocks Verilog/SystemVerilog Involving a Verilog dialect
#3230 opened May 28, 2022 by teqdruid
6
[HW][SV] Unpacked Struct HW Involving the `hw` dialect Verilog/SystemVerilog Involving a Verilog dialect
#2623 opened Feb 12, 2022 by uenoku
[SV] Move interfaces over to use InnerNameRef Verilog/SystemVerilog Involving a Verilog dialect
#2189 opened Nov 16, 2021 by fabianschuiki
[SV] Make InterfaceInstanceOp more like InterfaceOp Verilog/SystemVerilog Involving a Verilog dialect
#1464 opened Jul 22, 2021 by seldridge
2
[SV] Remove duplication of non-"wire-equivalent"/"free" operations in PrettifyVerilog Verilog/SystemVerilog Involving a Verilog dialect
#1418 opened Jul 14, 2021 by teqdruid
Using SystemVerilog Interfaces in Other Interfaces Verilog/SystemVerilog Involving a Verilog dialect
#1171 opened May 28, 2021 by seldridge
2
Add Module Prefix to Generated Verilog enhancement New feature or request ExportVerilog HW Involving the `hw` dialect Verilog/SystemVerilog Involving a Verilog dialect
#932 opened Apr 20, 2021 by seldridge SiFive-2
5
Add flag for SV v.s. V emission enhancement New feature or request Verilog/SystemVerilog Involving a Verilog dialect
#512 opened Jan 26, 2021 by darthscsi
2
ProTip! Updated in the last three days: updated:>2025-02-11.