ImportVerilog: add step-1 SV interface import#9904
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Hey @AmurG, thanks for kicking this off! I don't think we want to use any ops in the SV dialect in ImportVerilog. It's a bit counter-intuitive, but the SV dialect is intended for Verilog emission, but it doesn't preserve enough information for Verilog ingestion. The Moore dialect is where we deal with the ImportVerilog side of things. There is no interface support there yet, but @Mohamed-Khairy-SWE has been working towards some first support there (#9792). Could these two approaches be combined, or one built on the other?
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---This PR was based on AI-generated content---
This PR adds basic interface support for a total overhaul of the CIRCT frontend that supports UVM/Randomization well.
Kept intentionally small for basic interface/modport support and CI/human testing.