Big endianness Support added

README.md

@@ -119,6 +119,7 @@ For booting operating system images, see the information under the
 - Sv32, Sv39, Sv48 and Sv57 page-based virtual-memory systems
 - Svbare extension for Bare mode virtual-memory translation
 - Physical Memory Protection (PMP)
+- Endianness control
 
 <!-- Uncomment the following section when unratified extensions are added
 The following unratified extensions are supported and can be enabled using the `--enable-experimental-extensions` flag:

config/default.json

@@ -21,6 +21,9 @@
     },
     "translation": {
       "dirty_update": false
+    },
+    "endianness": {
+      "big_endian": true
     }
   },
   "platform": {

model/prelude.sail

@@ -236,6 +236,10 @@ type max_mem_access : Int = 4096
 // Type used for memory access widths. Zero byte accesses are not allowed.
 type mem_access_width = range(1, max_mem_access)
 
+// Function to reverse endianness.
+// Currently, not able to import reverse_endianness.sail library because of type compatibility issue.
+val reverse_endianness = pure {c: "reverse_endianness"} : forall 'n . bits(8 * 'n) -> bits(8 * 'n)
+
 // Enable unratified extensions
 val sys_enable_experimental_extensions = pure "sys_enable_experimental_extensions" : unit -> bool
 

model/riscv_mem.sail

@@ -80,8 +80,17 @@ function write_kind_of_flags (aq : bool, rl : bool, con : bool) -> write_kind =
     (true,  false, true)  => throw(Error_not_implemented("sc.aq"))
   }
 
+function get_endianness(typ : AccessType(ext_access_type)) -> Endianness = {
+    match (typ, effectivePrivilege(typ, mstatus, cur_privilege)) {
+      (InstructionFetch(), _)   => LittleEndian,
+      (_, Machine)     => if bits_to_bool(mstatus[MBE]) then BigEndian else LittleEndian,
+      (_, Supervisor)  => if bits_to_bool(mstatus[SBE]) then BigEndian else LittleEndian,
+      (_, User)        => if bits_to_bool(mstatus[UBE]) then BigEndian else LittleEndian,
+    }
+}
+
 // only used for actual memory regions, to avoid MMIO effects
-function phys_mem_read forall 'n, 0 < 'n <= max_mem_access . (t : AccessType(ext_access_type), paddr : physaddr, width : int('n), aq : bool, rl: bool, res : bool, meta : bool) -> MemoryOpResult((bits(8 * 'n), mem_meta)) = {
+function phys_mem_read forall 'n, 0 < 'n <= max_mem_access . (t : AccessType(ext_access_type), paddr : physaddr, width : int('n), aq : bool, rl: bool, res : bool, meta : bool, current_endianness: Endianness) -> MemoryOpResult((bits(8 * 'n), mem_meta)) = {
   let result = (match read_kind_of_flags(aq, rl, res) {
     Some(rk) => Some(read_ram(rk, paddr, width, meta)),
     None()   => None()
@@ -90,7 +99,10 @@ function phys_mem_read forall 'n, 0 < 'n <= max_mem_access . (t : AccessType(ext
     (InstructionFetch(), None()) => Err(E_Fetch_Access_Fault()),
     (Read(Data), None()) => Err(E_Load_Access_Fault()),
     (_,          None()) => Err(E_SAMO_Access_Fault()),
-    (_,      Some(v, m)) => Ok(v, m),
+    (_,      Some(v, m)) => {
+      let v = endianness_conversion(v, current_endianness);
+      Ok(v, m)
+    },
   }
 }
 
@@ -117,10 +129,10 @@ function checked_mem_read forall 'n, 0 < 'n <= max_mem_access . (
     Some(e) => Err(e),
     None() => {
       if   within_mmio_readable(paddr, width)
-      then MemoryOpResult_add_meta(mmio_read(t, paddr, width), default_meta)
+      then MemoryOpResult_add_meta(mmio_read(t, paddr, width, get_endianness(t)), default_meta)
       else if within_phys_mem(paddr, width)
       then match ext_check_phys_mem_read(t, paddr, width, aq, rl, res, meta) {
-        Ext_PhysAddr_OK()     => phys_mem_read(t, paddr, width, aq, rl, res, meta),
+        Ext_PhysAddr_OK()     => phys_mem_read(t, paddr, width, aq, rl, res, meta, get_endianness(t)),
         Ext_PhysAddr_Error(e) => Err(e)
       } else match t {
         InstructionFetch() => Err(E_Fetch_Access_Fault()),

model/riscv_platform.sail

@@ -24,6 +24,11 @@ val elf_entry = pure {
   c: "elf_entry"
 } : unit -> int
 
+function endianness_conversion forall 'n, 0 < 'n <= max_mem_access . (data : bits(8 * 'n), current_endianness: Endianness) -> bits(8 * 'n) =
+  match current_endianness {
+    LittleEndian => data,
+    BigEndian => reverse_endianness(data),
+  }
 
 // Cache block size is 2^cache_block_size_exp. Max is `max_mem_access` (4096)
 // because this model performs `cbo.zero` with a single write, and the behaviour
@@ -142,8 +147,17 @@ let MTIMECMP_BASE_HI : physaddrbits = zero_extend(0x04004)
 let MTIME_BASE       : physaddrbits = zero_extend(0x0bff8)
 let MTIME_BASE_HI    : physaddrbits = zero_extend(0x0bffc)
 
-val clint_load : forall 'n, 'n > 0. (AccessType(ext_access_type), physaddr, int('n)) -> MemoryOpResult(bits(8 * 'n))
-function clint_load(t, Physaddr(addr), width) = {
+val clint_load : forall 'n, 'n > 0. (AccessType(ext_access_type), physaddr, int('n), Endianness) -> MemoryOpResult(bits(8 * 'n))
+function clint_load(t, Physaddr(addr), width, current_endianness) = {
+  //these two registers are 64 bits, so simple conversion is not accurate.
+  //consider 0x78563412 stored at mtime/cmp and when reading in big endian format,
+  //we change it to 0x1234567800000000. So position for mtime and mtime_hi are reversed. (not for ld)
+  var converted_mtime    = endianness_conversion(mtime, current_endianness);
+  var converted_mtimecmp = endianness_conversion(mtimecmp, current_endianness);
+  if ((current_endianness == BigEndian) & 'n == 4) then {
+                converted_mtime    = converted_mtime[31..0] @ converted_mtime[63..32];
+                converted_mtimecmp = converted_mtimecmp[31..0] @ converted_mtimecmp[63..32];
+                };
   let addr = addr - plat_clint_base ();
   /* FIXME: For now, only allow exact aligned access. */
   if addr == MSIP_BASE & ('n == 8 | 'n == 4)
@@ -155,41 +169,41 @@ function clint_load(t, Physaddr(addr), width) = {
   else if addr == MTIMECMP_BASE & ('n == 4)
   then {
     if   get_config_print_platform()
-    then print_platform("clint<4>[" ^ BitStr(addr) ^ "] -> " ^ BitStr(mtimecmp[31..0]));
+    then print_platform("clint<4>[" ^ BitStr(addr) ^ "] -> " ^ BitStr(converted_mtimecmp[31..0]));
     /* FIXME: Redundant zero_extend currently required by Lem backend */
-    Ok(zero_extend(32, mtimecmp[31..0]))
+    Ok(zero_extend(32, converted_mtimecmp[31..0]))
   }
   else if addr == MTIMECMP_BASE & ('n == 8)
   then {
     if   get_config_print_platform()
-    then print_platform("clint<8>[" ^ BitStr(addr) ^ "] -> " ^ BitStr(mtimecmp));
+    then print_platform("clint<8>[" ^ BitStr(addr) ^ "] -> " ^ BitStr(converted_mtimecmp));
     /* FIXME: Redundant zero_extend currently required by Lem backend */
-    Ok(zero_extend(64, mtimecmp))
+    Ok(zero_extend(64, converted_mtimecmp))
   }
   else if addr == MTIMECMP_BASE_HI & ('n == 4)
   then {
     if   get_config_print_platform()
-    then print_platform("clint-hi<4>[" ^ BitStr(addr) ^ "] -> " ^ BitStr(mtimecmp[63..32]));
+    then print_platform("clint-hi<4>[" ^ BitStr(addr) ^ "] -> " ^ BitStr(converted_mtimecmp[63..32]));
     /* FIXME: Redundant zero_extend currently required by Lem backend */
-    Ok(zero_extend(32, mtimecmp[63..32]))
+    Ok(zero_extend(32, converted_mtimecmp[63..32]))
   }
   else if addr == MTIME_BASE & ('n == 4)
   then {
     if   get_config_print_platform()
-    then print_platform("clint[" ^ BitStr(addr) ^ "] -> " ^ BitStr(mtime));
-    Ok(zero_extend(32, mtime[31..0]))
+    then print_platform("clint[" ^ BitStr(addr) ^ "] -> " ^ BitStr(converted_mtime));
+    Ok(zero_extend(32, converted_mtime[31..0]))
   }
   else if addr == MTIME_BASE & ('n == 8)
   then {
     if   get_config_print_platform()
-    then print_platform("clint[" ^ BitStr(addr) ^ "] -> " ^ BitStr(mtime));
-    Ok(zero_extend(64, mtime))
+    then print_platform("clint[" ^ BitStr(addr) ^ "] -> " ^ BitStr(converted_mtime));
+    Ok(zero_extend(64, converted_mtime))
   }
   else if addr == MTIME_BASE_HI & ('n == 4)
   then {
     if   get_config_print_platform()
-    then print_platform("clint[" ^ BitStr(addr) ^ "] -> " ^ BitStr(mtime));
-    Ok(zero_extend(32, mtime[63..32]))
+    then print_platform("clint[" ^ BitStr(addr) ^ "] -> " ^ BitStr(converted_mtime));
+    Ok(zero_extend(32, converted_mtime[63..32]))
   }
   else {
     if   get_config_print_platform()
@@ -313,17 +327,20 @@ function reset_htif () -> unit = {
  * dispatched the address.
  */
 
-val htif_load : forall 'n, 'n > 0. (AccessType(ext_access_type), physaddr, int('n)) -> MemoryOpResult(bits(8 * 'n))
-function htif_load(t, Physaddr(paddr), width) = {
+val htif_load : forall 'n, 'n > 0. (AccessType(ext_access_type), physaddr, int('n), Endianness) -> MemoryOpResult(bits(8 * 'n))
+function htif_load(t, Physaddr(paddr), width, current_endianness) = {
+  var converted_htif_tohost = endianness_conversion(htif_tohost, current_endianness);
+  //htif_tohost is a 64 bit register, same logic as of mtime, mtimecmp for handling big endianness conversion.
+  if ((current_endianness == BigEndian) & width == 4) then converted_htif_tohost = converted_htif_tohost[31..0] @ converted_htif_tohost[63..32];
   if   get_config_print_platform()
-  then print_platform("htif[" ^ hex_bits_str(paddr) ^ "] -> " ^ BitStr(htif_tohost));
+  then print_platform("htif[" ^ hex_bits_str(paddr) ^ "] -> " ^ BitStr(converted_htif_tohost));
   /* FIXME: For now, only allow the expected access widths. */
   if      width == 8 & (paddr == plat_htif_tohost())
-  then    Ok(zero_extend(64, htif_tohost))         /* FIXME: Redundant zero_extend currently required by Lem backend */
+  then    Ok(zero_extend(64, converted_htif_tohost))         /* FIXME: Redundant zero_extend currently required by Lem backend */
   else if width == 4 & paddr == plat_htif_tohost()
-  then    Ok(zero_extend(32, htif_tohost[31..0]))  /* FIXME: Redundant zero_extend currently required by Lem backend */
+  then    Ok(zero_extend(32, converted_htif_tohost[31..0]))  /* FIXME: Redundant zero_extend currently required by Lem backend */
   else if width == 4 & paddr == plat_htif_tohost() + 4
-  then    Ok(zero_extend(32, htif_tohost[63..32])) /* FIXME: Redundant zero_extend currently required by Lem backend */
+  then    Ok(zero_extend(32, converted_htif_tohost[63..32])) /* FIXME: Redundant zero_extend currently required by Lem backend */
   else match t {
     InstructionFetch() => Err(E_Fetch_Access_Fault()),
     Read(Data) => Err(E_Load_Access_Fault()),
@@ -400,24 +417,25 @@ function within_mmio_writable forall 'n, 0 < 'n <= max_mem_access . (addr : phys
   then false
   else within_clint(addr, width) | (within_htif_writable(addr, width) & 'n <= 8)
 
-function mmio_read forall 'n, 0 < 'n <= max_mem_access . (t : AccessType(ext_access_type), paddr : physaddr, width : int('n)) -> MemoryOpResult(bits(8 * 'n)) =
+function mmio_read forall 'n, 0 < 'n <= max_mem_access . (t : AccessType(ext_access_type), paddr : physaddr, width : int('n), current_endianness : Endianness) -> MemoryOpResult(bits(8 * 'n)) =
   if   within_clint(paddr, width)
-  then clint_load(t, paddr, width)
+  then clint_load(t, paddr, width, current_endianness)
   else if within_htif_readable(paddr, width) & (1 <= 'n)
-  then htif_load(t, paddr, width)
+  then htif_load(t, paddr, width, current_endianness)
   else match t {
     InstructionFetch() => Err(E_Fetch_Access_Fault()),
     Read(Data) => Err(E_Load_Access_Fault()),
     _          => Err(E_SAMO_Access_Fault())
   }
 
-function mmio_write forall 'n, 0 <'n <= max_mem_access . (paddr : physaddr, width : int('n), data: bits(8 * 'n)) -> MemoryOpResult(bool) =
+function mmio_write forall 'n, 0 <'n <= max_mem_access . (paddr : physaddr, width : int('n), data: bits(8 * 'n)) -> MemoryOpResult(bool) = {
   if   within_clint(paddr, width)
   then clint_store(paddr, width, data)
   else if within_htif_writable(paddr, width) & 'n <= 8
   then htif_store(paddr, width, data)
   else Err(E_SAMO_Access_Fault())
 
+}
 /* Platform initialization and ticking. */
 
 function init_platform() -> unit = {

model/riscv_sys_control.sail

@@ -373,10 +373,7 @@ function reset_sys() -> unit = {
 
   // "If little-endian memory accesses are supported, the mstatus/mstatush field
   // MBE is reset to 0."
-  // TODO: The handling of mstatush is a bit awkward currently, but the model
-  // currently only supports little endian so MBE is always 0.
-  // See https://github.com/riscv/sail-riscv/issues/639
-  // mstatus[MBE] = 0b0;
+  mstatus[MBE] = 0b0;
 
   long_csr_write_callback("mstatus", "mstatush", mstatus.bits);
 

model/riscv_sys_regs.sail

@@ -85,6 +85,9 @@ register misa : Misa =
 /* whether misa is R/W */
 function sys_enable_writable_misa() -> bool = config base.writable_misa
 
+/* Whether Endianness Control is supported or not*/
+function big_endian_supported() -> bool = config memory.endianness.big_endian
+
 /* Whether FIOM bit of menvcfg/senvcfg is enabled. It must be enabled if
    supervisor mode is implemented and non-bare addressing modes are supported. */
 function sys_enable_writable_fiom() -> bool = config base.writable_fiom
@@ -197,6 +200,7 @@ bitfield Mstatus : bits(64) = {
   SPP  : 8,
 
   MPIE : 7,
+  UBE  : 6,
   SPIE : 5,
 
   MIE  : 3,
@@ -233,9 +237,8 @@ function legalize_mstatus(o : Mstatus, v : bits(64)) -> Mstatus = {
     // MPELP = v[MPELP],
     // MPV = v[MPV],
     // GVA = v[GVA],
-    /* We don't currently support changing MBE and SBE. */
-    // MBE = v[MBE],
-    // SBE = v[SBE],
+    MBE = if big_endian_supported() then v[MBE] else 0b0,
+    SBE = if (big_endian_supported() & currentlyEnabled(Ext_S)) then v[SBE] else 0b0,
     /* We don't support dynamic changes to SXL and UXL. */
     // SXL = if xlen == 64 then v[SXL] else o[SXL],
     // UXL = if xlen == 64 then v[UXL] else o[UXL],
@@ -259,6 +262,7 @@ function legalize_mstatus(o : Mstatus, v : bits(64)) -> Mstatus = {
     SPP = if currentlyEnabled(Ext_S) then v[SPP] else 0b0,
     VS = v[VS],
     MPIE = v[MPIE],
+    UBE = if (big_endian_supported() & currentlyEnabled(Ext_U)) then v[UBE] else 0b0,
     SPIE = if currentlyEnabled(Ext_S) then v[SPIE] else 0b0,
     MIE = v[MIE],
     SIE = if currentlyEnabled(Ext_S) then v[SIE] else 0b0,
@@ -689,6 +693,7 @@ bitfield Sstatus : bits(64) = {
   FS    : 14 .. 13,
   VS    : 10 .. 9,
   SPP   : 8,
+  UBE   : 6,
   SPIE  : 5,
   SIE   : 1,
 }
@@ -708,6 +713,7 @@ function lower_mstatus(m : Mstatus) -> Sstatus = {
     FS = m[FS],
     VS = m[VS],
     SPP = m[SPP],
+    UBE = m[UBE],
     SPIE = m[SPIE],
     SIE = m[SIE],
   ]
@@ -728,6 +734,7 @@ function lift_sstatus(m : Mstatus, s : Sstatus) -> Mstatus = {
     FS = s[FS],
     VS = s[VS],
     SPP = s[SPP],
+    UBE = s[UBE],
     SPIE = s[SPIE],
     SIE = s[SIE],
   ]

model/riscv_types.sail

@@ -302,6 +302,9 @@ enum extop_zbb = {SEXTB, SEXTH, ZEXTH}
 
 enum zicondop = {CZERO_EQZ, CZERO_NEZ}
 
+//Endianness type.
+enum Endianness = { BigEndian, LittleEndian }
+
 enum wrsop = {WRS_STO, WRS_NTO}
 
 enum WaitReason = {WAIT_WFI, WAIT_WRS_STO, WAIT_WRS_NTO}

model/riscv_vmem_utils.sail

@@ -246,6 +246,8 @@ function vmem_write(rs_addr, offset, width, data, acc, aq, rl, res) = {
   /* Get the address, X(rs_addr) (no offset).
    * Extensions might perform additional checks on address validity.
    */
+  let data = endianness_conversion(data, get_endianness(acc));
+
   let vaddr : virtaddr = match ext_data_get_addr(rs_addr, offset, acc, width) {
     Ext_DataAddr_OK(vaddr) => vaddr,
     Ext_DataAddr_Error(e)  => return Err(Ext_DataAddr_Check_Failure(e)),

test/first_party/CMakeLists.txt

@@ -85,6 +85,7 @@ set(tests
     "test_hello_world.c"
     "test_max_pmp.c"
     "test_minstret.S"
+    "test_endianness.S"
     "test_pmp_access.c"
 )