Add support for Zvkned.

Makefile.old

@@ -75,6 +75,8 @@ SAIL_DEFAULT_INST += riscv_insts_zvksh.sail
 SAIL_DEFAULT_INST += riscv_insts_zimop.sail
 SAIL_DEFAULT_INST += riscv_insts_zcmop.sail
 
+SAIL_DEFAULT_INST += riscv_insts_zvkned.sail
+
 SAIL_SEQ_INST  = $(SAIL_DEFAULT_INST) riscv_jalr_seq.sail
 SAIL_RMEM_INST = $(SAIL_DEFAULT_INST) riscv_jalr_rmem.sail riscv_insts_rmem.sail
 

README.md

@@ -108,6 +108,7 @@ For booting operating system images, see the information under the
 - Zvbb extension for vector basic bit-manipulation, v1.0
 - Zvbc extension for vector carryless multiplication, v1.0
 - Zvkb extension for vector cryptography bit-manipulation, v1.0
+- Zvkned extension for vector cryptography NIST Suite: Vector AES Block Cipher, v1.0
 - Zvknha and Zvknhb extensions for vector cryptography NIST Suite: Vector SHA-2 Secure Hash, v1.0
 - Zvksh extension for vector cryptography ShangMi Suite: SM3 Secure Hash, v1.0
 - Machine, Supervisor, and User modes

config/default.json

@@ -190,6 +190,9 @@
     "Zvbc": {
       "supported": true
     },
+    "Zvkned": {
+      "supported": true
+    },
     "Zvknha": {
       "supported": true
     },

model/CMakeLists.txt

@@ -89,6 +89,7 @@ foreach (xlen IN ITEMS 32 64)
                 "riscv_insts_zawrs.sail"
                 "riscv_insts_zvbb.sail"
                 "riscv_insts_zvbc.sail"
+                "riscv_insts_zvkned.sail"
                 "riscv_insts_zvknhab.sail"
                 "riscv_insts_zvksh.sail"
                 # Zimop and Zcmop should be at the end so they can be overridden by earlier extensions

model/riscv_extensions.sail

@@ -185,6 +185,9 @@ function clause hartSupports(Ext_Zvkb) = config extensions.Zvkb.supported
 // Vector Carryless Multiplication
 enum clause extension = Ext_Zvbc
 function clause hartSupports(Ext_Zvbc) = config extensions.Zvbc.supported
+// NIST Suite: Vector AES Block Cipher
+enum clause extension = Ext_Zvkned
+function clause hartSupports(Ext_Zvkned) = config extensions.Zvkned.supported
 // NIST Suite: Vector SHA-2 Secure Hash
 enum clause extension = Ext_Zvknha
 function clause hartSupports(Ext_Zvknha) = config extensions.Zvknha.supported
@@ -195,7 +198,6 @@ function clause hartSupports(Ext_Zvknhb) = config extensions.Zvknhb.supported
 enum clause extension = Ext_Zvksh
 function clause hartSupports(Ext_Zvksh) = config extensions.Zvksh.supported
 
-
 // Count Overflow and Mode-Based Filtering
 enum clause extension = Ext_Sscofpmf
 function clause hartSupports(Ext_Sscofpmf) = config extensions.Sscofpmf.supported

model/riscv_insts_vext_utils.sail

@@ -204,6 +204,17 @@ function write_velem_oct_vec(vd, SEW, input, i) = {
     write_single_element(SEW, 8 * i + j, vd, input[j]);
 }
 
+/* Extracts 4 consecutive vector elements starting from index 4*i and returns a vector */
+val get_velem_quad_vec : forall 'n 'm 'p, 'n > 0 & 8 <= 'm <= 64  & 'p >= 0 & 4 * 'p + 3 < 'n. (vector('n, bits('m)), int('p)) -> vector(4, bits('m))
+function get_velem_quad_vec(v, i) = [ v[4 * i + 3], v[4 * i + 2], v[4 * i + 1], v[4 * i] ]
+
+/* Writes each of the 4 elements from the input vector to the vector register vd, starting at position 4 * i */
+val write_velem_quad_vec : forall 'p 'n, 8 <= 'n <= 64 & 'p >= 0. (vregidx, int('n), vector(4, bits('n)), int('p)) -> unit
+function write_velem_quad_vec(vd, SEW, input, i) = {
+  foreach(j from 0 to 3)
+    write_single_element(SEW, 4 * i + j, vd, input[j]);
+}
+
 /* Get the starting element index from csr vtype */
 val get_start_element : unit -> result(nat, unit)
 function get_start_element() = {