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Add support for Zvksh extension #862

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nadime15
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Add following instructions:

vsm3me.vv
vsm3c.vi

Tested with riscv-vector-tests.

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github-actions bot commented Apr 16, 2025

Test Results

400 tests  ±0   400 ✅ ±0   1m 54s ⏱️ -1s
  1 suites ±0     0 💤 ±0 
  1 files   ±0     0 ❌ ±0 

Results for commit 010962e. ± Comparison against base commit 8ff2a70.

♻️ This comment has been updated with latest results.

@jordancarlin jordancarlin added the extension Adds support for a RISC-V extension label Apr 16, 2025
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@pmundkur pmundkur left a comment

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This is so much nicer than the existing spec! Just minor suggestions.

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One small nit, but looks great! A huge improvement from the version in the spec right now!

foreach (j from 16 to 23)
w[j] = zvk_sh_w(w[j - 16], w[j - 9], w[j - 3], w[j - 13], w[j - 6]);

write_velem_oct_vec(vd, SEW, vrev8([w[23], w[22], w[21], w[20], w[19], w[18], w[17], w[16]]), i);
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Might be clearer to break the vrev8 out into its own line before this. Kind of easy for it to get lost otherwise when reading through this function.

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In regard to this discussion. Would it make sense to do something like:

Suggested change
write_velem_oct_vec(vd, SEW, vrev8([w[23], w[22], w[21], w[20], w[19], w[18], w[17], w[16]]), i);
write_velem_oct_vec(vd, SEW,
vrev8([w[23], w[22], w[21], w[20], w[19], w[18], w[17], w[16]]), i);

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It's definitely better. Does it really not work writing it to an intermediate variable?

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Unfortunately not

what works is:

let 'm = 4;
let w_out : vector(8, bits('m * 8)) = vrev8([w[23], w[22], w[21], w[20], w[19], w[18], w[17], w[16]]);
write_velem_oct_vec(vd, SEW, w_out, i);

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Very nice code! Did any of it come from #248 (I'll add a co-authored-by if so)?

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@Timmmm yes some parts are from #248. I added @charmitro as a co-author in the first commit. Usually, I make a few commits during development, and then before merging, I squash everything into the first commit, with him listed as a co-author.

@nadime15 nadime15 force-pushed the ext_zvksh branch 2 times, most recently from ef87c0e to c05d468 Compare April 18, 2025 18:51
Co-authored-by: Charalampos Mitrodimas <[email protected]>
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@pmundkur I just noticed that this PR has two approvals, so we could theoretically merge it unless there is a reason not to. The Rocq build is currently failing, I am not sure whether this needs to be resolved before merging or if it is acceptable for now. Let me know what you think.

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bacam commented Apr 29, 2025

The Rocq output is failing because it isn't as clever as Sail about solving 'm * 8 == 'SEW problems when type checking the use of vrev8. I don't think there's an easy solution or workaround for this, so I suggest disabling the automatic Rocq check for now.

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5 participants