[FPSAN] Optimize shared MMA operand loads#10527
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Context: #10473 landed after #10572 removed the old sliced-layout helpers, so the restacked #10527 called getSingleDimSliceEncoding and expandAllSlicedDims and failed during compilation on every CI GPU job. Implementation: derive the K-axis range type with getSlicedTensorType and expand it with reshapeAndBroadcast, matching the replacement API introduced by #10572 while preserving the direct result layout. Validation: - ninja -C build/cmake.macosx-11.0-arm64-cpython-3.12 triton-opt -j8 - lit -v test/TritonGPU/nvidia-fpsan.mlir test/TritonGPU/fpsan.mlir
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PR description written by Codex Optimize i8 decomposition by reordering the dots and eagerly combining into the accumulator-on-the-fly to minimize register pressure, and include a basic subtiling heuristic determined experimentally ## Stack Merge bottom-up: - [x] #10472 - [x] #10473 - [x] #10527 - [x] #10532 - [ ] #10533 (this PR) - [ ] #10542 - [ ] #10548 - [ ] #10561 - [ ] #10559
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PR description written by Codex Fix FPSAN TMEM emulation for initialized scratch synchronization, predicated stores, reduction loads, and scale-copy reinterpret views. ## Stack Merge bottom-up: - [x] #10472 - [x] #10473 - [x] #10527 - [x] #10532 - [x] #10533 - [ ] #10542 (this PR) - [ ] #10548 - [ ] #10561 - [ ] #10559
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PR description written by Codex Remove redundant payload sign clears before masked multiplies so NVPTX cannot fold them to `abs.f32`, which quiets signaling NaNs. Add a reduced one-warp regression that fails bitwise on PR #10542’s base and passes with the fix. ## Stack Merge bottom-up: - [x] #10472 - [x] #10473 - [x] #10527 - [x] #10532 - [x] #10533 - [x] #10542 - [ ] #10548 (this PR) - [ ] #10561 - [ ] #10559
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PR description written by Codex
Load shared MMA operands directly into their result layouts and reuse existing scale shadows, avoiding redundant layout conversions and scale snapshots, and also load accumulator directly into its MMA layout.
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