Fix formatter abort on non-ANSI wire signed ports

[kbrunham-intel]

Summary

• Non-ANSI module body ports such as input wire signed [15:0] sig1 built kDataType children in reverse source order (signed before wire). The formatter walks CST order, so it CHECK-failed in the tree-unwrapper.
• Build those ports the same way as input bit signed: wrap net/var type then signing in kDataTypePrimitive so leaf visit order matches the file.
• Adds formatter regression tests for the original Check failure when using signed wires #2008 sample, plus verible-verilog-format crash for special wire signed vectors #2474, Crash of formatter on a signed wire #2063, logic signed, output/inout, and unsigned.

Fixes #2008
Fixes #2474
Fixes #2063

Test plan

• bazel test -c opt //verible/verilog/formatting:formatter_test //verible/verilog/CST:port_test //verible/verilog/CST:type_test //verible/verilog/parser:verilog-parser_test
• Original Check failure when using signed wires #2008, verible-verilog-format crash for special wire signed vectors #2474, and Crash of formatter on a signed wire #2063 samples format without aborting
• CI on this PR is green

[kbrunham-intel]

Hi @hzeller. Please consider this change. It addresses 3 cases filed for the formatter.