cpu/cyclonev_hps: Add Intel Cyclone V HPS (hard dual Cortex-A9) support

CHANGES.md

@@ -36,6 +36,8 @@
 * **litex/soc/integration/export**                 : Added wide CSR field helper support to generated software exports ([cc4a2542b](https://github.com/enjoy-digital/litex/commit/cc4a2542b)).
 * **litex/soc/cores/hyperbus / integration**       : Added native AXI/AXI-Lite HyperRAM support, automatic bus-standard argument selection, and a SoC-level `add_hyperram` helper ([53727e564](https://github.com/enjoy-digital/litex/commit/53727e564), [545985891](https://github.com/enjoy-digital/litex/commit/545985891), [d6a73d241](https://github.com/enjoy-digital/litex/commit/d6a73d241)).
 * **litex/soc/integration/soc**                    : Added slave-bus clock-domain crossing support and a SoC reset request hook ([4a8ae302e](https://github.com/enjoy-digital/litex/commit/4a8ae302e), [973351aa8](https://github.com/enjoy-digital/litex/commit/973351aa8)).
+* **litex/soc/cores/cpu/cyclonev_hps**             : Added Intel Cyclone V HPS (hard dual Cortex-A9) hardcore CPU support with H2F-LW/H2F AXI3 masters, F2H AXI3 slave, F2SDRAM Avalon-MM ports and F2H interrupts through direct `cyclonev_hps_interface_*` atom instantiation (no Qsys), targeting boards where the HPS is pre-booted (e.g. MiSTer/DE10-Nano), with GIC-aware BIOS interrupt support (Cortex-A9 exception vectors + GIC-390 mask/pending/dispatch).
+* **litex/soc/interconnect/avalon**                : Added `Wishbone2AvalonMM` bridge (Wishbone Slave to Avalon-MM Master, single-beat) with simulation coverage.
 * **litex/soc/cores/cpu**                          : Added Loongson GS232 and CDIM MIPS CPU integrations plus Linux toolchain/package support and boot coverage ([e90b7e8af](https://github.com/enjoy-digital/litex/commit/e90b7e8af), [b7ed16b19](https://github.com/enjoy-digital/litex/commit/b7ed16b19), [af19e210a](https://github.com/enjoy-digital/litex/commit/af19e210a), [060c51988](https://github.com/enjoy-digital/litex/commit/060c51988), [6e5982265](https://github.com/enjoy-digital/litex/commit/6e5982265), [4a3f398c2](https://github.com/enjoy-digital/litex/commit/4a3f398c2)).
 * **litex/sim / soc/cores/cpu/qemu**               : Added RISC-V QEMU co-simulation CPU support, AXI co-simulation bridge integration, LiteX simulation wiring, and smoke coverage ([b92b7f0f8](https://github.com/enjoy-digital/litex/commit/b92b7f0f8), [464df90e6](https://github.com/enjoy-digital/litex/commit/464df90e6), [6ff0f1560](https://github.com/enjoy-digital/litex/commit/6ff0f1560), [876ddf83e](https://github.com/enjoy-digital/litex/commit/876ddf83e), [da55d8846](https://github.com/enjoy-digital/litex/commit/da55d8846)).
 * **litex/soc/software/bios**                      : Added extensible boot-method registration, documented BIOS configuration flags, reported BIOS SRAM stack margin, and added an option to disable ANSI output ([c612a0194](https://github.com/enjoy-digital/litex/commit/c612a0194), [11a4ddfc0](https://github.com/enjoy-digital/litex/commit/11a4ddfc0), [11f94eaa6](https://github.com/enjoy-digital/litex/commit/11f94eaa6), [b26d1096d](https://github.com/enjoy-digital/litex/commit/b26d1096d)).

litex/soc/cores/cpu/cyclonev_hps/__init__.py

@@ -0,0 +1 @@
+from litex.soc.cores.cpu.cyclonev_hps.core import CycloneVHPS

litex/soc/cores/cpu/cyclonev_hps/boot-helper.c

@@ -0,0 +1,5 @@
+void boot_helper(unsigned long r1, unsigned long r2, unsigned long r3, unsigned long addr);
+
+void boot_helper(unsigned long r1, unsigned long r2, unsigned long r3, unsigned long addr) {
+    goto *(void*)addr;
+}