[PowerPC][AIX] Emit PowerPC version for XCOFF #95510

EsmeYi · 2024-06-14T07:10:42Z

With this PR, both assembly and object on AIX emit PPC versions.

llvmbot · 2024-06-14T07:11:03Z

@llvm/pr-subscribers-debuginfo
@llvm/pr-subscribers-llvm-binary-utilities
@llvm/pr-subscribers-mc
@llvm/pr-subscribers-objectyaml

@llvm/pr-subscribers-backend-powerpc

Author: Esme (EsmeYi)

Changes

With this PR, both assembly and object on AIX emit PPC versions.
Without setting -mcpu, the default value of PPC version is pwr7 on AIX.

Patch is 27.94 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/95510.diff

31 Files Affected:

(modified) llvm/include/llvm/BinaryFormat/XCOFF.h (+15-3)
(modified) llvm/include/llvm/MC/MCAssembler.h (+5)
(modified) llvm/include/llvm/MC/MCObjectStreamer.h (+1)
(modified) llvm/include/llvm/MC/MCStreamer.h (+3)
(modified) llvm/lib/BinaryFormat/XCOFF.cpp (+14)
(modified) llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp (+5)
(modified) llvm/lib/MC/MCAsmStreamer.cpp (+9)
(modified) llvm/lib/MC/MCObjectStreamer.cpp (+4)
(modified) llvm/lib/MC/MCStreamer.cpp (+1)
(modified) llvm/lib/MC/XCOFFObjectWriter.cpp (+2-5)
(modified) llvm/test/CodeGen/PowerPC/aix-extern-weak.ll (+1-2)
(modified) llvm/test/CodeGen/PowerPC/aix-extern.ll (+1-2)
(modified) llvm/test/CodeGen/PowerPC/aix-filename-c.ll (+54-9)
(modified) llvm/test/CodeGen/PowerPC/aix-filename-cpp.ll (+3-4)
(modified) llvm/test/CodeGen/PowerPC/aix-filename-f.ll (+3-4)
(modified) llvm/test/CodeGen/PowerPC/aix-func-dsc-gen.ll (+1-1)
(modified) llvm/test/CodeGen/PowerPC/aix-llvm-intrinsic.ll (+1-2)
(modified) llvm/test/CodeGen/PowerPC/aix-tls-xcoff-reloc-large.ll (+1-1)
(modified) llvm/test/CodeGen/PowerPC/aix-tls-xcoff-reloc.ll (+1-1)
(modified) llvm/test/CodeGen/PowerPC/aix-tls-xcoff-variables.ll (+1-1)
(modified) llvm/test/CodeGen/PowerPC/aix-weak.ll (+1-2)
(modified) llvm/test/CodeGen/PowerPC/aix-xcoff-data.ll (+4-4)
(modified) llvm/test/CodeGen/PowerPC/aix-xcoff-reloc.ll (+1-2)
(modified) llvm/test/DebugInfo/XCOFF/empty.ll (+2)
(modified) llvm/test/DebugInfo/XCOFF/explicit-section.ll (+1)
(modified) llvm/test/DebugInfo/XCOFF/function-sections.ll (+1)
(modified) llvm/test/tools/llvm-readobj/XCOFF/symbols-invalid.test (+1-1)
(modified) llvm/test/tools/llvm-readobj/XCOFF/symbols.test (+1-1)
(modified) llvm/test/tools/llvm-readobj/XCOFF/symbols64.test (+1-1)
(modified) llvm/test/tools/yaml2obj/XCOFF/aux-symbols.yaml (+6-6)
(modified) llvm/tools/llvm-readobj/XCOFFDumper.cpp (+14-1)

diff --git a/llvm/include/llvm/BinaryFormat/XCOFF.h b/llvm/include/llvm/BinaryFormat/XCOFF.h
index bbcd8a4f29ae9..5e8d30b991f45 100644
--- a/llvm/include/llvm/BinaryFormat/XCOFF.h
+++ b/llvm/include/llvm/BinaryFormat/XCOFF.h
@@ -334,9 +334,20 @@ enum CFileLangId : uint8_t {
 };
 
 enum CFileCpuId : uint8_t {
-  TCPU_PPC64 = 2, ///< PowerPC common architecture 64-bit mode.
-  TCPU_COM = 3,   ///< POWER and PowerPC architecture common.
-  TCPU_970 = 19   ///< PPC970 - PowerPC 64-bit architecture.
+  TCPU_INVALID = 0, ///< Invalid id - assumes POWER for old objects.
+  TCPU_PPC = 1,     ///< PowerPC common architecture 32 bit mode.
+  TCPU_PPC64 = 2,   ///< PowerPC common architecture 64-bit mode.
+  TCPU_COM = 3,     ///< POWER and PowerPC architecture common.
+  TCPU_PWR = 4,     ///< POWER common architecture objects.
+  TCPU_PWR5 = 18,   ///< PWR5 - PowerPC 64-bit architecture.
+  TCPU_970 = 19,    ///< PPC970 - PowerPC 64-bit architecture.
+  TCPU_PWR6 = 20,   ///< PWR6 - PowerPC 64-bit architecture.
+  TCPU_PWR5X = 22,  ///< PWR5+ - PowerPC 64-bit architecture.
+  TCPU_PWR6E = 23,  ///< PWR6E - PowerPC 64-bit architecture.
+  TCPU_PWR7 = 24,   ///< PWR7 - PowerPC 64-bit architecture.
+  TCPU_PWR8 = 25,   ///< PWR8 - PowerPC 64-bit architecture.
+  TCPU_PWR9 = 26,   ///< PWR9 - PowerPC 64-bit architecture.
+  TCPU_PWR10 = 27,  ///< PWR10 - PowerPC 64-bit architecture.
 };
 
 enum SymbolAuxType : uint8_t {
@@ -468,6 +479,7 @@ enum ExtendedTBTableFlag : uint8_t {
 
 StringRef getNameForTracebackTableLanguageId(TracebackTable::LanguageID LangId);
 SmallString<32> getExtendedTBTableFlagString(uint8_t Flag);
+XCOFF::CFileCpuId getCpuID(StringRef CPU);
 
 struct CsectProperties {
   CsectProperties(StorageMappingClass SMC, SymbolType ST)
diff --git a/llvm/include/llvm/MC/MCAssembler.h b/llvm/include/llvm/MC/MCAssembler.h
index 914c7506e754b..45f4befeb84d5 100644
--- a/llvm/include/llvm/MC/MCAssembler.h
+++ b/llvm/include/llvm/MC/MCAssembler.h
@@ -135,6 +135,8 @@ class MCAssembler {
   std::vector<std::pair<std::string, size_t>> FileNames;
   // Optional compiler version.
   std::string CompilerVersion;
+  // PPC CPU type.
+  StringRef CPU;
 
   MCDwarfLineTableParams LTParams;
 
@@ -490,6 +492,9 @@ class MCAssembler {
   }
   StringRef getCompilerVersion() { return CompilerVersion; }
 
+  void setCPU(StringRef TargetCPU) { CPU = TargetCPU; }
+  StringRef getCPU() { return CPU; }
+
   /// Write the necessary bundle padding to \p OS.
   /// Expects a fragment \p F containing instructions and its size \p FSize.
   void writeFragmentPadding(raw_ostream &OS, const MCEncodedFragment &F,
diff --git a/llvm/include/llvm/MC/MCObjectStreamer.h b/llvm/include/llvm/MC/MCObjectStreamer.h
index c0a337f5ea45e..c3d44e51e98db 100644
--- a/llvm/include/llvm/MC/MCObjectStreamer.h
+++ b/llvm/include/llvm/MC/MCObjectStreamer.h
@@ -203,6 +203,7 @@ class MCObjectStreamer : public MCStreamer {
   void emitFileDirective(StringRef Filename) override;
   void emitFileDirective(StringRef Filename, StringRef CompilerVersion,
                          StringRef TimeStamp, StringRef Description) override;
+  void emitMachineDirective(StringRef CPU) override;
 
   void emitAddrsig() override;
   void emitAddrsigSym(const MCSymbol *Sym) override;
diff --git a/llvm/include/llvm/MC/MCStreamer.h b/llvm/include/llvm/MC/MCStreamer.h
index b7468cf70a664..fa29c1dd5033d 100644
--- a/llvm/include/llvm/MC/MCStreamer.h
+++ b/llvm/include/llvm/MC/MCStreamer.h
@@ -908,6 +908,9 @@ class MCStreamer {
   virtual void emitFileDirective(StringRef Filename, StringRef CompilerVersion,
                                  StringRef TimeStamp, StringRef Description);
 
+  // Emit '.machine "CPU"' assembler diretive.
+  virtual void emitMachineDirective(StringRef CPU);
+
   /// Emit the "identifiers" directive.  This implements the
   /// '.ident "version foo"' assembler directive.
   virtual void emitIdent(StringRef IdentString) {}
diff --git a/llvm/lib/BinaryFormat/XCOFF.cpp b/llvm/lib/BinaryFormat/XCOFF.cpp
index 6b11ab2ff96bc..f2e3b2e82f950 100644
--- a/llvm/lib/BinaryFormat/XCOFF.cpp
+++ b/llvm/lib/BinaryFormat/XCOFF.cpp
@@ -9,6 +9,7 @@
 #include "llvm/BinaryFormat/XCOFF.h"
 #include "llvm/ADT/SmallString.h"
 #include "llvm/ADT/StringRef.h"
+#include "llvm/ADT/StringSwitch.h"
 #include "llvm/Support/Errc.h"
 #include "llvm/Support/Error.h"
 
@@ -107,6 +108,19 @@ StringRef XCOFF::getNameForTracebackTableLanguageId(
 }
 #undef LANG_CASE
 
+XCOFF::CFileCpuId XCOFF::getCpuID(StringRef CPU) {
+  return StringSwitch<XCOFF::CFileCpuId>(CPU)
+      .Case("pwr4", XCOFF::TCPU_PWR)
+      .Case("pwr5", XCOFF::TCPU_PWR5)
+      .Case("pwr6", XCOFF::TCPU_PWR6)
+      .Case("pwr5x", XCOFF::TCPU_PWR5X)
+      .Case("pwr7", XCOFF::TCPU_PWR7)
+      .Case("pwr8", XCOFF::TCPU_PWR8)
+      .Case("pwr9", XCOFF::TCPU_PWR9)
+      .Case("pwr10", XCOFF::TCPU_PWR10)
+      .Default(XCOFF::TCPU_PWR7);
+}
+
 Expected<SmallString<32>> XCOFF::parseParmsType(uint32_t Value,
                                                 unsigned FixedParmsNum,
                                                 unsigned FloatingParmsNum) {
diff --git a/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp b/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
index 3580d484b7ddd..f9a7c37b70bf2 100644
--- a/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
+++ b/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
@@ -517,6 +517,11 @@ bool AsmPrinter::doInitialization(Module &M) {
   // On AIX, emit bytes for llvm.commandline metadata after .file so that the
   // C_INFO symbol is preserved if any csect is kept by the linker.
   if (TM.getTargetTriple().isOSBinFormatXCOFF()) {
+    // Emit .machine directive on AIX.
+    StringRef TargetCPU =
+        TM.getTargetCPU().empty() ? "pwr7" : TM.getTargetCPU();
+    OutStreamer->emitMachineDirective(TargetCPU);
+
     emitModuleCommandLines(M);
     // Now we can generate section information.
     OutStreamer->initSections(false, *TM.getMCSubtargetInfo());
diff --git a/llvm/lib/MC/MCAsmStreamer.cpp b/llvm/lib/MC/MCAsmStreamer.cpp
index f257d0d9e83f7..4b6c52eb9f68a 100644
--- a/llvm/lib/MC/MCAsmStreamer.cpp
+++ b/llvm/lib/MC/MCAsmStreamer.cpp
@@ -272,6 +272,9 @@ class MCAsmStreamer final : public MCStreamer {
   void emitFileDirective(StringRef Filename) override;
   void emitFileDirective(StringRef Filename, StringRef CompilerVersion,
                          StringRef TimeStamp, StringRef Description) override;
+
+  void emitMachineDirective(StringRef CPU) override;
+
   Expected<unsigned> tryEmitDwarfFileDirective(
       unsigned FileNo, StringRef Directory, StringRef Filename,
       std::optional<MD5::MD5Result> Checksum = std::nullopt,
@@ -1610,6 +1613,12 @@ void MCAsmStreamer::emitFileDirective(StringRef Filename,
   EmitEOL();
 }
 
+void MCAsmStreamer::emitMachineDirective(StringRef CPU) {
+  OS << "\t.machine\t";
+  PrintQuotedString(CPU, OS);
+  EmitEOL();
+}
+
 void MCAsmStreamer::printDwarfFileDirective(
     unsigned FileNo, StringRef Directory, StringRef Filename,
     std::optional<MD5::MD5Result> Checksum, std::optional<StringRef> Source,
diff --git a/llvm/lib/MC/MCObjectStreamer.cpp b/llvm/lib/MC/MCObjectStreamer.cpp
index bf1ce76cdc14b..80c1a8920177f 100644
--- a/llvm/lib/MC/MCObjectStreamer.cpp
+++ b/llvm/lib/MC/MCObjectStreamer.cpp
@@ -902,6 +902,10 @@ void MCObjectStreamer::emitFileDirective(StringRef Filename,
   // with the integrated assembler.
 }
 
+void MCObjectStreamer::emitMachineDirective(StringRef CPU) {
+  getAssembler().setCPU(CPU);
+}
+
 void MCObjectStreamer::emitAddrsig() {
   getAssembler().getWriter().emitAddrsigSection();
 }
diff --git a/llvm/lib/MC/MCStreamer.cpp b/llvm/lib/MC/MCStreamer.cpp
index 199d865ea3496..c248cc5002ea5 100644
--- a/llvm/lib/MC/MCStreamer.cpp
+++ b/llvm/lib/MC/MCStreamer.cpp
@@ -1171,6 +1171,7 @@ void MCStreamer::emitFileDirective(StringRef Filename,
                                    StringRef CompilerVersion,
                                    StringRef TimeStamp, StringRef Description) {
 }
+void MCStreamer::emitMachineDirective(StringRef CPU) {}
 void MCStreamer::emitCOFFSymbolStorageClass(int StorageClass) {
   llvm_unreachable("this directive only supported on COFF targets");
 }
diff --git a/llvm/lib/MC/XCOFFObjectWriter.cpp b/llvm/lib/MC/XCOFFObjectWriter.cpp
index a7c3818d598b7..c059b98212f62 100644
--- a/llvm/lib/MC/XCOFFObjectWriter.cpp
+++ b/llvm/lib/MC/XCOFFObjectWriter.cpp
@@ -1193,11 +1193,8 @@ void XCOFFObjectWriter::writeSymbolTable(MCAssembler &Asm,
       LangID = XCOFF::TB_Fortran;
     else
       LangID = XCOFF::TB_CPLUSPLUS;
-    uint8_t CpuID;
-    if (is64Bit())
-      CpuID = XCOFF::TCPU_PPC64;
-    else
-      CpuID = XCOFF::TCPU_COM;
+
+    uint8_t CpuID = XCOFF::getCpuID(Asm.getCPU());
 
     int NumberOfFileAuxEntries = 1;
     if (!Vers.empty())
diff --git a/llvm/test/CodeGen/PowerPC/aix-extern-weak.ll b/llvm/test/CodeGen/PowerPC/aix-extern-weak.ll
index ea61fdb022b5c..ab62cd95ae2a4 100644
--- a/llvm/test/CodeGen/PowerPC/aix-extern-weak.ll
+++ b/llvm/test/CodeGen/PowerPC/aix-extern-weak.ll
@@ -69,8 +69,7 @@ declare extern_weak void @foo_ext_weak(ptr)
 ; CHECKSYM-NEXT:     Value (SymbolTableIndex): 0x0
 ; CHECKSYM-NEXT:     Section: N_DEBUG
 ; CHECKSYM-NEXT:     Source Language ID: TB_CPLUSPLUS (0x9)
-; CHECKSYM32-NEXT:   CPU Version ID: TCPU_COM (0x3)
-; CHECKSYM64-NEXT:   CPU Version ID: TCPU_PPC64 (0x2)
+; CHECKSYM-NEXT:     CPU Version ID: TCPU_PWR (0x4)
 ; CHECKSYM-NEXT:     StorageClass: C_FILE (0x67)
 ; CHECKSYM-NEXT:     NumberOfAuxEntries: 2
 ; CHECKSYM:        Symbol {
diff --git a/llvm/test/CodeGen/PowerPC/aix-extern.ll b/llvm/test/CodeGen/PowerPC/aix-extern.ll
index b4366dddedb2f..825e30242ed50 100644
--- a/llvm/test/CodeGen/PowerPC/aix-extern.ll
+++ b/llvm/test/CodeGen/PowerPC/aix-extern.ll
@@ -92,8 +92,7 @@ declare i32 @bar_extern(ptr)
 ; CHECKSYM-NEXT:     Value (SymbolTableIndex): 0x0
 ; CHECKSYM-NEXT:     Section: N_DEBUG
 ; CHECKSYM-NEXT:     Source Language ID: TB_CPLUSPLUS (0x9)
-; CHECKSYM32-NEXT:   CPU Version ID: TCPU_COM (0x3)
-; CHECKSYM64-NEXT:   CPU Version ID: TCPU_PPC64 (0x2)
+; CHECKSYM-NEXT:     CPU Version ID: TCPU_PWR (0x4)
 ; CHECKSYM-NEXT:     StorageClass: C_FILE (0x67)
 ; CHECKSYM-NEXT:     NumberOfAuxEntries: 2
 ; CHECKSYM:        Symbol {
diff --git a/llvm/test/CodeGen/PowerPC/aix-filename-c.ll b/llvm/test/CodeGen/PowerPC/aix-filename-c.ll
index c4202a0c58cee..dd342c00176f3 100644
--- a/llvm/test/CodeGen/PowerPC/aix-filename-c.ll
+++ b/llvm/test/CodeGen/PowerPC/aix-filename-c.ll
@@ -1,12 +1,57 @@
-; RUN: llc -verify-machineinstrs -mtriple powerpc-ibm-aix-xcoff -filetype=obj -o %t.o < %s
-; RUN: llvm-readobj --symbols %t.o | FileCheck --check-prefixes=OBJ,OBJ32 %s
-; RUN: llc -verify-machineinstrs -mtriple powerpc64-ibm-aix-xcoff -filetype=obj -o %t64.o < %s
-; RUN: llvm-readobj --symbols %t64.o | FileCheck --check-prefixes=OBJ,OBJ64 %s
+; RUN: llc -verify-machineinstrs -mtriple powerpc64-ibm-aix-xcoff -mcpu=pwr9  < %s | FileCheck --check-prefixes=ASM %s
+
+; RUN: llc -verify-machineinstrs -mtriple powerpc-ibm-aix-xcoff -mcpu=pwr9 -filetype=obj -o %t.o < %s
+; RUN: llvm-readobj --symbols %t.o | FileCheck --check-prefixes=OBJ32 %s
+; RUN: llc -verify-machineinstrs -mtriple powerpc64-ibm-aix-xcoff -mcpu=pwr9 -filetype=obj -o %t64.o < %s
+; RUN: llvm-readobj --symbols %t64.o | FileCheck --check-prefixes=OBJ64 %s
 
 source_filename = "1.c"
 
-; OBJ: Name: .file
-; OBJ: Source Language ID: TB_C (0x0)
-; OBJ32: CPU Version ID: TCPU_COM (0x3)
-; OBJ64: CPU Version ID: TCPU_PPC64 (0x2)
-; OBJ: Name: 1.c
+; ASM:      .file   "1.c",,"LLVM version 19.0.0git"
+; ASM-NEXT: .machine   "pwr9"
+; ASM-NEXT: .csect ..text..[PR],5
+; ASM-NEXT: .rename	..text..[PR],""
+
+; OBJ32:      Symbol {
+; OBJ32-NEXT:   Index: 0
+; OBJ32-NEXT:   Name: .file
+; OBJ32-NEXT:   Value (SymbolTableIndex): 0x0
+; OBJ32-NEXT:   Section: N_DEBUG
+; OBJ32-NEXT:   Source Language ID: TB_C (0x0)
+; OBJ32-NEXT:   CPU Version ID: TCPU_PWR9 (0x1A)
+; OBJ32-NEXT:   StorageClass: C_FILE (0x67)
+; OBJ32-NEXT:   NumberOfAuxEntries: 2
+; OBJ32-NEXT:   File Auxiliary Entry {
+; OBJ32-NEXT:     Index: 1
+; OBJ32-NEXT:     Name: 1.c
+; OBJ32-NEXT:     Type: XFT_FN (0x0)
+; OBJ32-NEXT:   }
+; OBJ32-NEXT:   File Auxiliary Entry {
+; OBJ32-NEXT:     Index: 2
+; OBJ32-NEXT:     Name: LLVM version 19.0.0git
+; OBJ32-NEXT:     Type: XFT_CV (0x2)
+; OBJ32-NEXT:   }
+; OBJ32-NEXT: }
+
+; OBJ64:      Symbol {
+; OBJ64-NEXT:   Index: 0
+; OBJ64-NEXT:   Name: .file
+; OBJ64-NEXT:   Value (SymbolTableIndex): 0x0
+; OBJ64-NEXT:   Section: N_DEBUG
+; OBJ64-NEXT:   Source Language ID: TB_C (0x0)
+; OBJ64-NEXT:   CPU Version ID: TCPU_PWR9 (0x1A)
+; OBJ64-NEXT:   StorageClass: C_FILE (0x67)
+; OBJ64-NEXT:   NumberOfAuxEntries: 2
+; OBJ64-NEXT:   File Auxiliary Entry {
+; OBJ64-NEXT:     Index: 1
+; OBJ64-NEXT:     Name: 1.c
+; OBJ64-NEXT:     Type: XFT_FN (0x0)
+; OBJ64-NEXT:     Auxiliary Type: AUX_FILE (0xFC)
+; OBJ64-NEXT:   }
+; OBJ64-NEXT:   File Auxiliary Entry {
+; OBJ64-NEXT:     Index: 2
+; OBJ64-NEXT:     Name: LLVM version 19.0.0git
+; OBJ64-NEXT:     Type: XFT_CV (0x2)
+; OBJ64-NEXT:     Auxiliary Type: AUX_FILE (0xFC)
+; OBJ64-NEXT:   }
+; OBJ64-NEXT: }
diff --git a/llvm/test/CodeGen/PowerPC/aix-filename-cpp.ll b/llvm/test/CodeGen/PowerPC/aix-filename-cpp.ll
index 802281b6c1eaa..873619d20cd2c 100644
--- a/llvm/test/CodeGen/PowerPC/aix-filename-cpp.ll
+++ b/llvm/test/CodeGen/PowerPC/aix-filename-cpp.ll
@@ -1,12 +1,11 @@
 ; RUN: llc -verify-machineinstrs -mtriple powerpc-ibm-aix-xcoff -filetype=obj -o %t.o < %s
-; RUN: llvm-readobj --symbols %t.o | FileCheck --check-prefixes=OBJ,OBJ32 %s
+; RUN: llvm-readobj --symbols %t.o | FileCheck --check-prefixes=OBJ %s
 ; RUN: llc -verify-machineinstrs -mtriple powerpc64-ibm-aix-xcoff -filetype=obj -o %t64.o < %s
-; RUN: llvm-readobj --symbols %t64.o | FileCheck --check-prefixes=OBJ,OBJ64 %s
+; RUN: llvm-readobj --symbols %t64.o | FileCheck --check-prefixes=OBJ %s
 
 source_filename = "1.cpp"
 
 ; OBJ: Name: .file
 ; OBJ: Source Language ID: TB_CPLUSPLUS (0x9)
-; OBJ32: CPU Version ID: TCPU_COM (0x3)
-; OBJ64: CPU Version ID: TCPU_PPC64 (0x2)
+; OBJ: CPU Version ID: TCPU_PWR7 (0x18)
 ; OBJ: Name: 1.cpp
diff --git a/llvm/test/CodeGen/PowerPC/aix-filename-f.ll b/llvm/test/CodeGen/PowerPC/aix-filename-f.ll
index 99036bde702d6..1167148d21a7f 100644
--- a/llvm/test/CodeGen/PowerPC/aix-filename-f.ll
+++ b/llvm/test/CodeGen/PowerPC/aix-filename-f.ll
@@ -1,12 +1,11 @@
 ; RUN: llc -verify-machineinstrs -mtriple powerpc-ibm-aix-xcoff -filetype=obj -o %t.o < %s
-; RUN: llvm-readobj --symbols %t.o | FileCheck --check-prefixes=OBJ,OBJ32 %s
+; RUN: llvm-readobj --symbols %t.o | FileCheck --check-prefixes=OBJ %s
 ; RUN: llc -verify-machineinstrs -mtriple powerpc64-ibm-aix-xcoff -filetype=obj -o %t64.o < %s
-; RUN: llvm-readobj --symbols %t64.o | FileCheck --check-prefixes=OBJ,OBJ64 %s
+; RUN: llvm-readobj --symbols %t64.o | FileCheck --check-prefixes=OBJ %s
 
 source_filename = "1.f95"
 
 ; OBJ: Name: .file
 ; OBJ: Source Language ID: TB_Fortran (0x1)
-; OBJ32: CPU Version ID: TCPU_COM (0x3)
-; OBJ64: CPU Version ID: TCPU_PPC64 (0x2)
+; OBJ: CPU Version ID: TCPU_PWR7 (0x18)
 ; OBJ: Name: 1.f95
diff --git a/llvm/test/CodeGen/PowerPC/aix-func-dsc-gen.ll b/llvm/test/CodeGen/PowerPC/aix-func-dsc-gen.ll
index 4cca1b4d6f7ba..50221acc2b3ad 100644
--- a/llvm/test/CodeGen/PowerPC/aix-func-dsc-gen.ll
+++ b/llvm/test/CodeGen/PowerPC/aix-func-dsc-gen.ll
@@ -17,7 +17,7 @@ entry:
 ; CHECK-NEXT:     Value (SymbolTableIndex): 0x0
 ; CHECK-NEXT:     Section: N_DEBUG
 ; CHECK-NEXT:     Source Language ID: TB_CPLUSPLUS (0x9)
-; CHECK-NEXT:     CPU Version ID: TCPU_COM (0x3)
+; CHECK-NEXT:     CPU Version ID: TCPU_PWR7 (0x18)
 ; CHECK-NEXT:     StorageClass: C_FILE (0x67)
 ; CHECK-NEXT:     NumberOfAuxEntries: 2
 ; CHECK-NEXT:     File Auxiliary Entry {
diff --git a/llvm/test/CodeGen/PowerPC/aix-llvm-intrinsic.ll b/llvm/test/CodeGen/PowerPC/aix-llvm-intrinsic.ll
index 50677f36e3f7a..dc849c4f8933f 100644
--- a/llvm/test/CodeGen/PowerPC/aix-llvm-intrinsic.ll
+++ b/llvm/test/CodeGen/PowerPC/aix-llvm-intrinsic.ll
@@ -44,8 +44,7 @@ declare void @llvm.memset.p0.i32(ptr nocapture writeonly, i8, i32, i1 immarg)
 ; CHECKSYM-NEXT:     Value (SymbolTableIndex): 0x0
 ; CHECKSYM-NEXT:     Section: N_DEBUG
 ; CHECKSYM-NEXT:     Source Language ID: TB_CPLUSPLUS (0x9)
-; CHECKSYM32-NEXT:   CPU Version ID: TCPU_COM (0x3)
-; CHECKSYM64-NEXT:   CPU Version ID: TCPU_PPC64 (0x2)
+; CHECKSYM-NEXT:     CPU Version ID: TCPU_PWR (0x4)
 ; CHECKSYM-NEXT:     StorageClass: C_FILE (0x67)
 ; CHECKSYM-NEXT:     NumberOfAuxEntries: 2
 ; CHECKSYM:   }
diff --git a/llvm/test/CodeGen/PowerPC/aix-tls-xcoff-reloc-large.ll b/llvm/test/CodeGen/PowerPC/aix-tls-xcoff-reloc-large.ll
index 63d927391936c..d943d9bd6cf10 100644
--- a/llvm/test/CodeGen/PowerPC/aix-tls-xcoff-reloc-large.ll
+++ b/llvm/test/CodeGen/PowerPC/aix-tls-xcoff-reloc-large.ll
@@ -215,7 +215,7 @@ entry:
 ; SYM-NEXT:     Value (SymbolTableIndex): 0x0
 ; SYM-NEXT:     Section: N_DEBUG
 ; SYM-NEXT:     Source Language ID: TB_CPLUSPLUS (0x9)
-; SYM-NEXT:     CPU Version ID: TCPU_COM (0x3)
+; SYM-NEXT:     CPU Version ID: TCPU_PWR (0x4)
 ; SYM-NEXT:     StorageClass: C_FILE (0x67)
 ; SYM-NEXT:     NumberOfAuxEntries: 2
 ; SYM-NEXT:     File Auxiliary Entry {
diff --git a/llvm/test/CodeGen/PowerPC/aix-tls-xcoff-reloc.ll b/llvm/test/CodeGen/PowerPC/aix-tls-xcoff-reloc.ll
index c17b038a6960c..db1e770e04a1e 100644
--- a/llvm/test/CodeGen/PowerPC/aix-tls-xcoff-reloc.ll
+++ b/llvm/test/CodeGen/PowerPC/aix-tls-xcoff-reloc.ll
@@ -176,7 +176,7 @@ entry:
 ; SYM-NEXT:     Value (SymbolTableIndex): 0x0
 ; SYM-NEXT:     Section: N_DEBUG
 ; SYM-NEXT:     Source Language ID: TB_CPLUSPLUS (0x9)
-; SYM-NEXT:     CPU Version ID: TCPU_COM (0x3)
+; SYM-NEXT:     CPU Version ID: TCPU_PWR (0x4)
 ; SYM-NEXT:     StorageClass: C_FILE (0x67)
 ; SYM-NEXT:     NumberOfAuxEntries: 2
 ; SYM:        Symbol {
diff --git a/llvm/test/CodeGen/PowerPC/aix-tls-xcoff-variables.ll b/llvm/test/CodeGen/PowerPC/aix-tls-xcoff-variables.ll
index f9a1a61617761..3c84aa1225d2e 100644
--- a/llvm/test/CodeGen/PowerPC/aix-tls-xcoff-variables.ll
+++ b/llvm/test/CodeGen/PowerPC/aix-tls-xcoff-variables.ll
@@ -70,7 +70,7 @@
 ; SYMS-NEXT:     Value (SymbolTableIndex): 0x0
 ; SYMS-NEXT:     Section: N_DEBUG
 ; SYMS-NEXT:     Source Language ID: TB_CPLUSPLUS (0x9)
-; SYMS-NEXT:     CPU Version ID: TCPU_COM (0x3)
+; SYMS-NEXT:     CPU Version ID: TCPU_PWR7 (0x18)
 ; SYMS-NEXT:     StorageClass: C_FILE (0x67)
 ; SYMS-NEXT:     NumberOfAuxEntries: 2
 ; SYMS:         Symbol {
diff --git a/llvm/test/CodeGen/PowerPC/aix-weak.ll b/llvm/test/CodeGen/PowerPC/aix-weak.ll
index 7bf80ad19e9e0..3387eef8e43cb 100644
--- a/llvm/test/CodeGen/PowerPC/aix-weak.ll
+++ b/llvm/test/CodeGen/PowerPC/aix-weak.ll
@@ -104,8 +104,7 @@ entry:
 ; CHECKSYM-NEXT:     Value (SymbolTableIndex): 0x0
 ; CHECKSYM-NEXT:     Section: N_DEBUG
 ; CHECKSYM-NEXT:     Source Language ID: TB_CPLUSPLUS (0x9)
-; CHECKSYM32-NEXT:   CPU Version ID: TCPU_COM (0x3)
-; CHECKSYM64-NEXT:   CPU Version ID: TCPU_PPC64 (0x2)
+; CHECKSYM-NEXT:     CPU Version ID: TCPU_PWR (0x4)
 ; CHECKSYM-NEXT:     StorageClass: C_FILE (0x67)
 ; CHECKSYM-NEXT:     NumberOfAuxEntries: 2
 ; CHECKSYM:        Symbol {
diff --git a/llvm/test/CodeGen/PowerPC/aix-xcoff-data.ll b/llvm/test/CodeGen/PowerPC/aix-xcoff-data.ll
index de937386b8b7d..e28751f10a12f 100644
--- a/llvm/test/CodeGen/PowerPC/aix-xcoff-data.ll
+++ b/llvm/test/CodeGen/PowerPC/aix-xcoff-data.ll
@@ -45,8 +45,9 @@
 
 ; CHECK-NOT: .toc
 
-; CHECK:  .file
-; CHECK-NEXT:      .csect ..text..[PR],5
+; CHECK:      .file
+; CHECK-NEXT: .machine "pwr7"
+; CHECK-NEXT: .csect ..text..[PR],5
 
 ; CHECK:      .csect .data[RW],5
 ; CHECK-NEXT: .globl  ivar
@@ -212,8 +213,7 @@
 ; SYMS-NEXT:     Value (SymbolTableIndex): 0x0
 ; SYMS-NEXT:     Section: N_DEBUG
 ; SYMS-NEXT:     Source Language ID: TB_CPLUSPLUS (0x9)
-; SYMS32-NEXT:   CPU Version ID: TCPU_COM (0x3)
-; SYMS64-NEXT:   CPU Version ID: TCPU_PPC64 (0x2)
+; SYMS-NEXT:     CPU Version ID: TCPU_PWR7 (0x18)
 ; SYMS-NEXT:     StorageClass: C_FILE (0x67)
 ; SYMS-NEXT:     NumberOfAuxEntries: 2
 ; SYMS-NEXT:     File Auxiliary Entry {
diff --git a/llvm/test/CodeGen/PowerPC/aix-xcoff-reloc.ll b/llvm/test/CodeGen/PowerPC/aix-xcoff-reloc.ll
index 6599debbd41b4..541b3b1c19c05 100644
--- a/llvm/test/CodeGen/PowerPC/aix-xcoff-reloc.ll
+++ b/llvm/test/CodeGen/PowerPC/aix-xcoff-reloc.ll
@@ -163,8 +163,7 @@ declare i32 @b...
[truncated]

github-actions · 2024-06-14T07:13:29Z

✅ With the latest revision this PR passed the C/C++ code formatter.

bzEq · 2024-06-14T07:17:28Z

llvm/include/llvm/BinaryFormat/XCOFF.h

-  TCPU_PPC64 = 2, ///< PowerPC common architecture 64-bit mode.
-  TCPU_COM = 3,   ///< POWER and PowerPC architecture common.
-  TCPU_970 = 19   ///< PPC970 - PowerPC 64-bit architecture.
+  TCPU_INVALID = 0, ///< Invalid id - assumes POWER for old objects.


Is there any document where do these constants come from?

Yes, these values are found in the file /usr/include/aouthdr.h on AIX.

nit: Maybe you can add a comments to say that these definitions are from AIX OS headers? So that we know that these are XCOFF specific.

llvm/include/llvm/MC/MCAssembler.h

llvm/include/llvm/MC/MCStreamer.h

bzEq · 2024-06-14T07:23:13Z

llvm/test/CodeGen/PowerPC/aix-filename-c.ll

-; OBJ32: CPU Version ID: TCPU_COM (0x3)
-; OBJ64: CPU Version ID: TCPU_PPC64 (0x2)
-; OBJ: Name: 1.c
+; ASM:      .file   "1.c",,"LLVM version 19.0.0git"


What if LLVM version bumps up?

LLVM version is saved in auxiliary file symbol with the type of XFT_CV. If the string is longer than 8 bytes, it will be written in string table. It was added in #80162.

bzEq · 2024-06-14T07:23:37Z

llvm/test/CodeGen/PowerPC/aix-filename-c.ll

+; OBJ32-NEXT:   }
+; OBJ32-NEXT:   File Auxiliary Entry {
+; OBJ32-NEXT:     Index: 2
+; OBJ32-NEXT:     Name: LLVM version 19.0.0git


jh7370 · 2024-06-14T07:59:36Z

llvm/include/llvm/MC/MCAssembler.h

@@ -135,6 +135,8 @@ class MCAssembler {
  std::vector<std::pair<std::string, size_t>> FileNames;
  // Optional compiler version.
  std::string CompilerVersion;
+  // PPC CPU type.
+  StringRef CPU;


I would strongly advise this be a std::string, not a StringRef. Otherwise, the source of the value must be around in memory for the entire lifetime of this object (or at least as long as the CPU member might be referenced). It might come from some constant literal currently, but in the future, that might not be the case.

Changed, thanks!

llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp

chenzheng1030 · 2024-06-17T09:21:06Z

llvm/lib/BinaryFormat/XCOFF.cpp

+      .Case("pwr8", XCOFF::TCPU_PWR8)
+      .Case("pwr9", XCOFF::TCPU_PWR9)
+      .Case("pwr10", XCOFF::TCPU_PWR10)
+      .Default(XCOFF::TCPU_PWR7);


We need a better mapping for clang supports CPUs:

generic, 440, 450, 601, 602, 603, 603e, 603ev, 604, 604e, 620, 630, g3, 7400, g4, 7450, g4+, 750, 8548, 970, g5, a2, e500, e500mc, e5500, power3, pwr3, power4, pwr4, power5, pwr5, power5x, pwr5x, power6, pwr6, power6x, pwr6x, power7, pwr7, power8, pwr8, power9, pwr9, power10, pwr10, powerpc, ppc, ppc32, powerpc64, ppc64, powerpc64le, ppc64le, future

and the .machine supports CPUs:

#define TCPU_INVALID 0 /* Invalid id - assumes POWER for old objects */ #define TCPU_PPC 1 /* PowerPC common architecture 32 bit mode */ #define TCPU_PPC64 2 /* PowerPC common architecture 64 bit mode */ #define TCPU_COM 3 /* POWER and PowerPC architecture common */ #define TCPU_PWR 4 /* POWER common architecture objects */ #define TCPU_ANY 5 /* Mixture of any incompatable POWER */ /* and PowerPC architecture implementations */ #define TCPU_601 6 /* 601 implementation of PowerPC architecture */ #define TCPU_603 7 /* 603 implementation of PowerPC architecture */ #define TCPU_604 8 /* 604 implementation of PowerPC architecture */ #define TCPU_PWR1 10 /* RS1 implementation of POWER architecture */ #define TCPU_620 16 /* 620 - PowerPC 64-bit architecture */ #define TCPU_A35 17 /* A35 - PowerPC 64-bit architecture */ #define TCPU_PWR5 18 /* PWR5 - PowerPC 64-bit architecture */ #define TCPU_970 19 /* PPC970 - PowerPC 64-bit architecture */ #define TCPU_PWR6 20 /* PWR6 - PowerPC 64-bit architecture */ #define TCPU_VEC 21 /* PowerPC 64-bit arch with Vector Extension */ #define TCPU_PWR5X 22 /* PWR5+ - PowerPC 64-bit architecture */ #define TCPU_PWR6E 23 /* PWR6E - PowerPC 64-bit architecture */ #define TCPU_PWR7 24 /* PWR7 - PowerPC 64-bit architecture */ #define TCPU_PWR8 25 /* PWR8 - PowerPC 64-bit architecture */ #define TCPU_PWR9 26 /* PWR9 - PowerPC 64-bit architecture */ #define TCPU_PWR10 27 /* PWR10 - PowerPC 64-bit architecture */ #define TCPU_PWRX 224 /* RS2 implementation of POWER architecture */

Now the list seems not complete. Or at least we should explicit list all the CPUs supported by our product page https://www.ibm.com/docs/en/openxl-c-and-cpp-aix/17.1.2?topic=options-mcpu

llvm/include/llvm/MC/MCStreamer.h

ecnelises · 2024-06-21T10:12:08Z

llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp

+    // Walk through the target-cpu attribute of functions and use the newest
+    // level as the CPU of the module.
+    for (auto &F : M) {
+      StringRef FunCPU = TM.getSubtargetImpl(F)->getCPU();


What does FunCPU mean?

target-cpu attribute in functions

ecnelises · 2024-06-21T10:13:24Z

llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp

+      else
+        TargetCPU = "any";
+    }
+    OutStreamer->emitMachineDirective(TargetCPU);


AIX system as does not recognize power* names, can we assume here the target CPU is only supported form?

Valid values are:COM PWR PWR2 PPC 601 603 604 PPC64 620 A35 PWR4 PWR5 PWR5X 970 PPC970 PWR6 PWR6E PWR7 PWR8 PWR9 PWR10 ANY

Thanks. The valid values for the assembler are not exactly the same as those in XCOFF, so I thought it would be appropriate to support an intersection of them.

ecnelises · 2024-06-21T10:14:44Z

llvm/test/CodeGen/PowerPC/aix-cpu-version.ll

+; RUN: llc -verify-machineinstrs -mtriple powerpc64-ibm-aix-xcoff  < %s | FileCheck %s
+
+; CHECK:      .file "1.c"
+; CHECK-NEXT: .machine "ppc64"


Does system as's ppc64 and LLVM's ppc64 refer to the same instruction set?

EsmeYi · 2024-07-02T03:29:29Z

gentle ping

jh7370 · 2024-07-02T07:25:48Z

Sorry, this isn't something I'm interested in reviewing: I don't know have appropriate domain knowledge for it, nor the time to get up to speed on the area of CodeGen etc that this impacts. For the record, I see nothing objectionable in the small changes to llvm-readobj.

MaskRay · 2024-07-02T07:35:57Z

llvm/include/llvm/BinaryFormat/XCOFF.h

+  TCPU_601 = 6,     ///< 601 implementation of PowerPC architecture.
+  TCPU_603 = 7,     ///< 603 implementation of PowerPC architecture.
+  TCPU_604 = 8,     ///< 604 implementation of PowerPC architecture.
+  TCPU_620 = 16,    ///< 620  - PowerPC 64-bit architecture.


You can add a // The below are 64-bit architectures instead of duplicating the string for each enum member.

EsmeYi · 2024-07-02T07:37:03Z

Sorry, this isn't something I'm interested in reviewing: I don't know have appropriate domain knowledge for it, nor the time to get up to speed on the area of CodeGen etc that this impacts. For the record, I see nothing objectionable in the small changes to llvm-readobj.

Thank you James.

chenzheng1030 · 2024-07-05T09:38:15Z

llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp

+      if (!TM.getTargetCPU().empty())
+        TargetCpuId = XCOFF::getCpuID(TM.getTargetCPU());
+      else
+        TargetCpuId = XCOFF::TCPU_ANY;


Maybe TCPU_COM is a better default CPU type

chenzheng1030 · 2024-07-05T09:40:46Z

llvm/test/CodeGen/PowerPC/aix-func-dsc-gen.ll

@@ -27,7 +27,7 @@ entry:
 ; CHECK-NEXT:     }
 ; CHECK-NEXT:     File Auxiliary Entry {
 ; CHECK-NEXT:       Index: 2
-; CHECK-NEXT:       Name: LLVM
+; CHECK-NEXT:       Name: {{.*}}LLVM{{.*}}


Out of curious, why this is changed?

any ideas why this place is changed?

chenzheng1030 · 2024-07-05T09:43:39Z

llvm/test/tools/llvm-readobj/XCOFF/symbols64.test

@@ -145,7 +145,7 @@ Symbols:
 # SYMBOL64-NEXT:     Value (SymbolTableIndex): 0x0
 # SYMBOL64-NEXT:     Section: N_DEBUG
 # SYMBOL64-NEXT:     Source Language ID: TB_C (0x0)
-# SYMBOL64-NEXT:     CPU Version ID: 0x0
+# SYMBOL64-NEXT:     CPU Version ID: TCPU_INVALID (0x0)


Can we use a more meaningful default CPU version ID? TCPU_INVALID sounds not good to me. Maybe we can also use TCPU_COM

This field is omitted in yaml, therefore the value written into XCOFF is zero by default, which corresponds to TCPU_INVALID. I don't think we should make llvm-readobj print a value that doesn't match what it actually is?

Yes, you are right, we should not make yaml input and readobj output mismatch. I meant we can change the YAML input. But if that's not trivial, we can leave it for now.

chenzheng1030 · 2024-07-05T09:44:55Z

llvm/lib/MC/MCStreamer.cpp

@@ -1171,6 +1171,7 @@ void MCStreamer::emitFileDirective(StringRef Filename,
                                   StringRef CompilerVersion,
                                   StringRef TimeStamp, StringRef Description) {
 }
+void MCStreamer::emitMachineDirective(StringRef CPU) {}


nit: maybe we can also add llvm_unreachable like below line 1176

chenzheng1030 · 2024-07-05T09:49:18Z

llvm/lib/BinaryFormat/XCOFF.cpp

@@ -107,6 +108,61 @@ StringRef XCOFF::getNameForTracebackTableLanguageId(
 }
 #undef LANG_CASE

+XCOFF::CFileCpuId XCOFF::getCpuID(StringRef CPU) {
+  return StringSwitch<XCOFF::CFileCpuId>(CPU)
+      .Case("generic", XCOFF::TCPU_PWR7)


clang generic is not pwr7 actually. You can map it to TCPU_COM

chenzheng1030 · 2024-07-05T09:53:08Z

llvm/include/llvm/BinaryFormat/XCOFF.h

-  TCPU_PPC64 = 2, ///< PowerPC common architecture 64-bit mode.
-  TCPU_COM = 3,   ///< POWER and PowerPC architecture common.
-  TCPU_970 = 19   ///< PPC970 - PowerPC 64-bit architecture.
+  TCPU_INVALID = 0, ///< Invalid id - assumes POWER for old objects.


nit: Maybe you can add a comments to say that these definitions are from AIX OS headers? So that we know that these are XCOFF specific.

chenzheng1030 · 2024-07-05T10:12:12Z

llvm/lib/BinaryFormat/XCOFF.cpp

+      .Case("601", XCOFF::TCPU_601)
+      .Cases("602", "603", "603e", "603ev", XCOFF::TCPU_603)
+      .Cases("604", "604e", XCOFF::TCPU_604)
+      .Case("620", XCOFF::TCPU_620)


I don't think we need to handle names like power10 or ppc32 or powerpc which are all not supported by aix system assembler.

You can just add a statement here to say that the cpu names will be normalized by https://github.com/llvm/llvm-project/blob/main/clang/lib/Driver/ToolChains/Arch/PPC.cpp#L54-L77 in previous logic.

I continue to improve that normalization in #97541

The aix system supports:

Valid values are:COM PWR PWR2 PPC 601 603 604 PPC64 620 A35 PWR4 PWR5 PWR5X 970 PPC970 PWR6 PWR6E PWR7 PWR8 PWR9 PWR10 ANY

We may need to map some other normalized CPU names like a2,g5 or others to some know value like COM.

#97541 now is committed. We can adjust here accordingly.

Addressed. Thanks!

chenzheng1030 · 2024-07-05T10:13:35Z

llvm/lib/BinaryFormat/XCOFF.cpp

+      .Cases("pwr8", "power8", "PWR8", XCOFF::TCPU_PWR8)
+      .Cases("pwr9", "power9", "PWR9", XCOFF::TCPU_PWR9)
+      .Cases("pwr10", "power10", "PWR10", XCOFF::TCPU_PWR10)
+      .Cases("powerpc", "ppc", "ppc32", XCOFF::TCPU_ANY)


I verified with AIX system assembler, ppc32 will be generated as COM and so does PPC64.

chenzheng1030 · 2024-07-05T10:13:59Z

llvm/lib/BinaryFormat/XCOFF.cpp

+      .Cases("pwr9", "power9", "PWR9", XCOFF::TCPU_PWR9)
+      .Cases("pwr10", "power10", "PWR10", XCOFF::TCPU_PWR10)
+      .Cases("powerpc", "ppc", "ppc32", XCOFF::TCPU_ANY)
+      .Cases("powerpc64", "ppc64", "powerpc64le", "ppc64le", "PPC64",


PPC64LE is actually pwr8 in CLANG

chenzheng1030 · 2024-07-05T10:16:41Z

llvm/lib/BinaryFormat/XCOFF.cpp

+      .Cases("powerpc", "ppc", "ppc32", XCOFF::TCPU_ANY)
+      .Cases("powerpc64", "ppc64", "powerpc64le", "ppc64le", "PPC64",
+             XCOFF::TCPU_ANY)
+      .Cases("any", "ANY", "future", XCOFF::TCPU_ANY)


future may be changed from time to time. For now it is pwr10, but we will change it to pwr11 in a short time. Maybe a better fix is calling normalizeCPUName() in pr #97541, that PR is a concentrated place to normalize future to the right one. So in future, when future is changed, we only need to change that normalization function.

EsmeYi · 2024-07-20T15:01:45Z

Addressed parts of comments.
Will update after #97541 merged, where the function getNormalizedPPCTuneCPU() can be called in llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp and the XCOFF::getCpuID() will be updated then.

chenzheng1030 · 2024-07-26T08:57:17Z

llvm/test/tools/llvm-readobj/XCOFF/symbols64.test

@@ -145,7 +145,7 @@ Symbols:
 # SYMBOL64-NEXT:     Value (SymbolTableIndex): 0x0
 # SYMBOL64-NEXT:     Section: N_DEBUG
 # SYMBOL64-NEXT:     Source Language ID: TB_C (0x0)
-# SYMBOL64-NEXT:     CPU Version ID: 0x0
+# SYMBOL64-NEXT:     CPU Version ID: TCPU_INVALID (0x0)


Yes, you are right, we should not make yaml input and readobj output mismatch. I meant we can change the YAML input. But if that's not trivial, we can leave it for now.

chenzheng1030 · 2024-07-26T08:58:43Z

llvm/lib/BinaryFormat/XCOFF.cpp

+      .Case("601", XCOFF::TCPU_601)
+      .Cases("602", "603", "603e", "603ev", XCOFF::TCPU_603)
+      .Cases("604", "604e", XCOFF::TCPU_604)
+      .Case("620", XCOFF::TCPU_620)


#97541 now is committed. We can adjust here accordingly.

chenzheng1030 · 2024-07-26T09:00:15Z

llvm/include/llvm/BinaryFormat/XCOFF.h

+  TCPU_PWR8 = 25,
+  TCPU_PWR9 = 26,
+  TCPU_PWR10 = 27,
+


PWR11 is recently added.

I checked /usr/include/aouthdr.h on an AIX7.2 machine and didn't find the PWR11. Did I miss something?

chenzheng1030 · 2024-07-26T09:00:45Z

llvm/lib/BinaryFormat/XCOFF.cpp

+             XCOFF::TCPU_COM)
+      .Cases("ppc64le", "powerpc64le", XCOFF::TCPU_PWR8)
+      .Cases("any", "ANY", XCOFF::TCPU_ANY)
+      .Case("future", XCOFF::TCPU_PWR10)


future is not pwr10 now.

I didn't see the CPU ID for PWR11 defined in the header file on AIX.

chenzheng1030 · 2024-07-26T09:02:12Z

llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp

+      if (!TM.getTargetCPU().empty())
+        TargetCpuId = XCOFF::getCpuID(TM.getTargetCPU());
+      else
+        TargetCpuId = XCOFF::TCPU_COM;


if there is no -mcpu option either, maybe we should get the default CPU by calling to getNormalizedPPCTargetCPU() instead of setting it to XCOFF::TCPU_COM?

chenzheng1030 · 2024-07-26T09:06:35Z

llvm/test/CodeGen/PowerPC/aix-func-dsc-gen.ll

@@ -27,7 +27,7 @@ entry:
 ; CHECK-NEXT:     }
 ; CHECK-NEXT:     File Auxiliary Entry {
 ; CHECK-NEXT:       Index: 2
-; CHECK-NEXT:       Name: LLVM
+; CHECK-NEXT:       Name: {{.*}}LLVM{{.*}}


any ideas why this place is changed?

This PR emits implements the ability to emit the PPC version for both assembly and object files on AIX. Furthermore, this PR is intended to be a commandeered version of Esme's previous PR: llvm#95510

amy-kwan · 2024-10-21T20:25:55Z

FYI: I have created a new version of this PR at #113214 (intended to commandeer this PR).

This PR emits implements the ability to emit the PPC version for both assembly and object files on AIX. Furthermore, this PR is intended to be a commandeered version of Esme's previous PR: llvm#95510

EsmeYi added the backend:PowerPC label Jun 14, 2024

EsmeYi requested review from bzEq, chenzheng1030, ecnelises, diggerlin, jh7370 and stephenpeckham June 14, 2024 07:10

EsmeYi self-assigned this Jun 14, 2024

llvmbot added debuginfo mc Machine (object) code objectyaml llvm:binary-utilities labels Jun 14, 2024

bzEq reviewed Jun 14, 2024

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jh7370 reviewed Jun 14, 2024

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daltenty reviewed Jun 14, 2024

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llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp Outdated Show resolved Hide resolved

bzEq changed the title ~~[PowerPC][AIX] Emit PowerPC version for XCOFF.~~ [PowerPC][AIX] Emit PowerPC version for XCOFF Jun 15, 2024

chenzheng1030 reviewed Jun 17, 2024

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ecnelises reviewed Jun 21, 2024

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EsmeYi requested review from daltenty, bzEq, ecnelises, jh7370 and chenzheng1030 July 2, 2024 03:28

MaskRay reviewed Jul 2, 2024

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chenzheng1030 reviewed Jul 5, 2024

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chenzheng1030 reviewed Jul 26, 2024

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Rebase. (Comments are not addressed.)

e7938e9

EsmeYi force-pushed the esme/ppc_version branch from 0bd58dc to e7938e9 Compare August 8, 2024 02:09

Addressed comments.

760f247

amy-kwan mentioned this pull request Oct 21, 2024

[PowerPC][AIX] Emit PowerPC version for XCOFF #113214

Merged

[PowerPC][AIX] Emit PowerPC version for XCOFF #95510

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[PowerPC][AIX] Emit PowerPC version for XCOFF #95510

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amy-kwan commented Oct 21, 2024

EsmeYi commented Jun 14, 2024 •

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llvmbot commented Jun 14, 2024 •

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github-actions bot commented Jun 14, 2024 •

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