Big endianness Support added

README.md

@@ -118,6 +118,7 @@ Supported RISC-V ISA features
 - Svinval extension for fine-grained address-translation cache invalidation, v1.0
 - Sv32, Sv39, Sv48 and Sv57 page-based virtual-memory systems
 - Physical Memory Protection (PMP)
+- Big Endianness
 
 **For a list of unsupported extensions and features, see the [Extension Roadmap](https://github.com/riscv/sail-riscv/wiki/Extension-Roadmap).**
 

model/prelude.sail

@@ -237,3 +237,6 @@ type max_mem_access : Int = 4096
 
 // Type used for memory access widths. Zero byte accesses are not allowed.
 type mem_access_width = range(1, max_mem_access)
+
+// Function to reverse endianness.
+val reverse_endianness = pure {c: "reverse_endianness"} : forall 'n . bits(8 * 'n) -> bits(8 * 'n)

model/riscv_mem.sail

@@ -63,6 +63,17 @@ function write_kind_of_flags (aq : bool, rl : bool, con : bool) -> write_kind =
     (true,  false, true)  => throw(Error_not_implemented("sc.aq"))
   }
 
+function is_big_endian(typ : AccessType(ext_access_type)) -> bool = {
+    match effectivePrivilege(typ, mstatus, cur_privilege) {
+      Machine     => bits_to_bool(mstatus[MBE]),
+      Supervisor  => bits_to_bool(mstatus[SBE]),
+      User        => bits_to_bool(mstatus[UBE]),
+    }
+}
+
+function endianness_conversion forall 'n, 0 < 'n <= max_mem_access . (data : bits(8 * 'n), ac : AccessType(ext_access_type)) -> bits(8 * 'n) =
+  if is_big_endian(ac) & not(ac == Execute()) then reverse_endianness(data) else data
+
 // only used for actual memory regions, to avoid MMIO effects
 function phys_mem_read forall 'n, 0 < 'n <= max_mem_access . (t : AccessType(ext_access_type), paddr : physaddr, width : int('n), aq : bool, rl: bool, res : bool, meta : bool) -> MemoryOpResult((bits(8 * 'n), mem_meta)) = {
   let result = (match read_kind_of_flags(aq, rl, res) {
@@ -73,9 +84,11 @@ function phys_mem_read forall 'n, 0 < 'n <= max_mem_access . (t : AccessType(ext
     (Execute(),  None()) => Err(E_Fetch_Access_Fault()),
     (Read(Data), None()) => Err(E_Load_Access_Fault()),
     (_,          None()) => Err(E_SAMO_Access_Fault()),
-    (_,      Some(v, m)) => { if   get_config_print_mem()
-                              then print_mem("mem[" ^ to_str(t) ^ "," ^ BitStr(physaddr_bits(paddr)) ^ "] -> " ^ BitStr(v));
-                              Ok(v, m) }
+    (_,      Some(v, m)) => {
+                        let v = endianness_conversion(v, t);
+                        if   get_config_print_mem()
+                        then print_mem("mem[" ^ to_str(t) ^ "," ^ BitStr(physaddr_bits(paddr)) ^ "] -> " ^ BitStr(v));
+                        Ok(v, m) }
   }
 }
 
@@ -196,6 +209,7 @@ $endif
 
 // only used for actual memory regions, to avoid MMIO effects
 function phys_mem_write forall 'n, 0 < 'n <= max_mem_access . (wk : write_kind, paddr : physaddr, width : int('n), data : bits(8 * 'n), meta : mem_meta) -> MemoryOpResult(bool) = {
+  let data = endianness_conversion(data, Write());
   let result = write_ram(wk, paddr, width, data, meta);
   if   get_config_print_mem()
   then print_mem("mem[" ^ BitStr(physaddr_bits(paddr)) ^ "] <- " ^ BitStr(data));

model/riscv_sys_control.sail

@@ -341,10 +341,7 @@ function reset_sys() -> unit = {
 
   // "If little-endian memory accesses are supported, the mstatus/mstatush field
   // MBE is reset to 0."
-  // TODO: The handling of mstatush is a bit awkward currently, but the model
-  // currently only supports little endian so MBE is always 0.
-  // See https://github.com/riscv/sail-riscv/issues/639
-  // mstatus[MBE] = 0b0;
+  mstatus[MBE] = 0b0;
 
   // "The misa register is reset to enable the maximal set of supported extensions"
   reset_misa();

model/riscv_sys_regs.sail

@@ -207,6 +207,7 @@ bitfield Mstatus : bits(64) = {
   SPP  : 8,
 
   MPIE : 7,
+  UBE  : 6,
   SPIE : 5,
 
   MIE  : 3,
@@ -243,9 +244,8 @@ function legalize_mstatus(o : Mstatus, v : bits(64)) -> Mstatus = {
     // MPELP = v[MPELP],
     // MPV = v[MPV],
     // GVA = v[GVA],
-    /* We don't currently support changing MBE and SBE. */
-    // MBE = v[MBE],
-    // SBE = v[SBE],
+    MBE = v[MBE],
+    SBE = if extensionEnabled(Ext_S) then v[SBE] else 0b0,
     /* We don't support dynamic changes to SXL and UXL. */
     // SXL = if xlen == 64 then v[SXL] else o[SXL],
     // UXL = if xlen == 64 then v[UXL] else o[UXL],
@@ -269,6 +269,7 @@ function legalize_mstatus(o : Mstatus, v : bits(64)) -> Mstatus = {
     SPP = if extensionEnabled(Ext_S) then v[SPP] else 0b0,
     VS = v[VS],
     MPIE = v[MPIE],
+    UBE = if extensionEnabled(Ext_U) then v[UBE] else 0b0,
     SPIE = if extensionEnabled(Ext_S) then v[SPIE] else 0b0,
     MIE = v[MIE],
     SIE = if extensionEnabled(Ext_S) then v[SIE] else 0b0,
@@ -294,6 +295,7 @@ register mstatus : Mstatus = {
 }
 
 mapping clause csr_name_map = 0x300  <-> "mstatus"
+mapping clause csr_name_map = 0x310  <-> "mstatush"
 
 function clause is_CSR_defined(0x300) = true // mstatus
 function clause is_CSR_defined(0x310) = xlen == 32 // mstatush
@@ -726,6 +728,7 @@ bitfield Sstatus : bits(64) = {
   FS    : 14 .. 13,
   VS    : 10 .. 9,
   SPP   : 8,
+  UBE   : 6,
   SPIE  : 5,
   SIE   : 1,
 }
@@ -745,6 +748,7 @@ function lower_mstatus(m : Mstatus) -> Sstatus = {
     FS = m[FS],
     VS = m[VS],
     SPP = m[SPP],
+    UBE = m[UBE],
     SPIE = m[SPIE],
     SIE = m[SIE],
   ]
@@ -765,6 +769,7 @@ function lift_sstatus(m : Mstatus, s : Sstatus) -> Mstatus = {
     FS = s[FS],
     VS = s[VS],
     SPP = s[SPP],
+    UBE = s[UBE],
     SPIE = s[SPIE],
     SIE = s[SIE],
   ]