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Remove explicit type annotations and redundant type variables in Vector code #835

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611 changes: 256 additions & 355 deletions model/riscv_insts_vext_arith.sail
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270 changes: 104 additions & 166 deletions model/riscv_insts_vext_fp.sail
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29 changes: 10 additions & 19 deletions model/riscv_insts_vext_fp_red.sail
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Original file line number Diff line number Diff line change
Expand Up @@ -37,16 +37,12 @@ function process_rfvv_single(funct6, vm, vs2, vs1, vd, num_elem_vs, SEW, LMUL_po

if unsigned(vl) == 0 then return RETIRE_SUCCESS; /* if vl=0, no operation is performed */

let 'n = num_elem_vs;
let 'd = num_elem_vd;
let 'm = SEW;
let vm_val = read_vmask(num_elem_vs, vm, zvreg);
let vd_val = read_vreg(num_elem_vd, SEW, 0, vd);
let vs2_val = read_vreg(num_elem_vs, SEW, LMUL_pow, vs2);
let mask = init_masked_source(num_elem_vs, LMUL_pow, vm_val);

let vm_val : bits('n) = read_vmask(num_elem_vs, vm, zvreg);
let vd_val : vector('d, bits('m)) = read_vreg(num_elem_vd, SEW, 0, vd);
let vs2_val : vector('n, bits('m)) = read_vreg(num_elem_vs, SEW, LMUL_pow, vs2);
let mask : bits('n) = init_masked_source(num_elem_vs, LMUL_pow, vm_val);

var sum : bits('m) = read_single_element(SEW, 0, vs1); /* vs1 regardless of LMUL setting */
var sum = read_single_element(SEW, 0, vs1); /* vs1 regardless of LMUL setting */
foreach (i from 0 to (num_elem_vs - 1)) {
if mask[i] == bitone then {
sum = match funct6 {
Expand Down Expand Up @@ -79,17 +75,12 @@ function process_rfvv_widen(funct6, vm, vs2, vs1, vd, num_elem_vs, SEW, LMUL_pow

if unsigned(vl) == 0 then return RETIRE_SUCCESS; /* if vl=0, no operation is performed */

let 'n = num_elem_vs;
let 'd = num_elem_vd;
let 'm = SEW;
let 'o = SEW_widen;

let vm_val : bits('n) = read_vmask(num_elem_vs, vm, zvreg);
let vd_val : vector('d, bits('o)) = read_vreg(num_elem_vd, SEW_widen, 0, vd);
let vs2_val : vector('n, bits('m)) = read_vreg(num_elem_vs, SEW, LMUL_pow, vs2);
let mask : bits('n) = init_masked_source(num_elem_vs, LMUL_pow, vm_val);
let vm_val = read_vmask(num_elem_vs, vm, zvreg);
let vd_val = read_vreg(num_elem_vd, SEW_widen, 0, vd);
let vs2_val = read_vreg(num_elem_vs, SEW, LMUL_pow, vs2);
let mask = init_masked_source(num_elem_vs, LMUL_pow, vm_val);

var sum : bits('o) = read_single_element(SEW_widen, 0, vs1); /* vs1 regardless of LMUL setting */
var sum = read_single_element(SEW_widen, 0, vs1); /* vs1 regardless of LMUL setting */
foreach (i from 0 to (num_elem_vs - 1)) {
if mask[i] == bitone then {
/* currently ordered/unordered sum reductions do the same operations */
Expand Down
22 changes: 8 additions & 14 deletions model/riscv_insts_vext_fp_vm.sail
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Expand Up @@ -35,13 +35,10 @@ function clause execute(FVVMTYPE(funct6, vm, vs2, vs1, vd)) = {
if illegal_fp_vd_unmasked(SEW, rm_3b) then { handle_illegal(); return RETIRE_FAIL };
assert(SEW != 8);

let 'n = num_elem;
let 'm = SEW;

let vm_val : bits('n) = read_vmask(num_elem, vm, zvreg);
let vs1_val : vector('n, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1);
let vs2_val : vector('n, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2);
let vd_val : bits('n) = read_vmask(num_elem, 0b0, vd);
let vm_val = read_vmask(num_elem, vm, zvreg);
let vs1_val = read_vreg(num_elem, SEW, LMUL_pow, vs1);
let vs2_val = read_vreg(num_elem, SEW, LMUL_pow, vs2);
let vd_val = read_vmask(num_elem, 0b0, vd);

let (initial_result, mask) = init_masked_result_cmp(num_elem, SEW, LMUL_pow, vd_val, vm_val);
var result = initial_result;
Expand Down Expand Up @@ -99,13 +96,10 @@ function clause execute(FVFMTYPE(funct6, vm, vs2, rs1, vd)) = {
if illegal_fp_vd_unmasked(SEW, rm_3b) then { handle_illegal(); return RETIRE_FAIL };
assert(SEW != 8);

let 'n = num_elem;
let 'm = SEW;

let vm_val : bits('n) = read_vmask(num_elem, vm, zvreg);
let rs1_val : bits('m) = get_scalar_fp(rs1, 'm);
let vs2_val : vector('n, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2);
let vd_val : bits('n) = read_vmask(num_elem, 0b0, vd);
let vm_val = read_vmask(num_elem, vm, zvreg);
let rs1_val = get_scalar_fp(rs1, SEW);
let vs2_val = read_vreg(num_elem, SEW, LMUL_pow, vs2);
let vd_val = read_vmask(num_elem, 0b0, vd);

let (initial_result, mask) = init_masked_result_cmp(num_elem, SEW, LMUL_pow, vd_val, vm_val);
var result = initial_result;
Expand Down
66 changes: 21 additions & 45 deletions model/riscv_insts_vext_mask.sail
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Expand Up @@ -36,12 +36,9 @@ function clause execute(MMTYPE(funct6, vs2, vs1, vd)) = {

if illegal_vd_unmasked() then { handle_illegal(); return RETIRE_FAIL };

let 'n = num_elem;
let 'm = SEW;

let vs1_val : bits('n) = read_vmask(num_elem, 0b0, vs1);
let vs2_val : bits('n) = read_vmask(num_elem, 0b0, vs2);
let vd_val : bits('n) = read_vmask(num_elem, 0b0, vd);
let vs1_val = read_vmask(num_elem, 0b0, vs1);
let vs2_val = read_vmask(num_elem, 0b0, vs2);
let vd_val = read_vmask(num_elem, 0b0, vd);

let (initial_result, mask) = init_masked_result_carry(num_elem, SEW, 0, vd_val);
var result = initial_result;
Expand Down Expand Up @@ -94,11 +91,8 @@ function clause execute(VCPOP_M(vm, vs2, rd)) = {

if illegal_vd_unmasked() | not(assert_vstart(0)) then { handle_illegal(); return RETIRE_FAIL };

let 'n = num_elem;
let 'm = SEW;

let vm_val : bits('n) = read_vmask(num_elem, vm, zvreg);
let vs2_val : bits('n) = read_vmask(num_elem, 0b0, vs2);
let vm_val = read_vmask(num_elem, vm, zvreg);
let vs2_val = read_vmask(num_elem, 0b0, vs2);

let (_, mask) = init_masked_result_cmp(num_elem, SEW, 0, vs2_val, vm_val);

Expand Down Expand Up @@ -129,11 +123,8 @@ function clause execute(VFIRST_M(vm, vs2, rd)) = {

if illegal_vd_unmasked() | not(assert_vstart(0)) then { handle_illegal(); return RETIRE_FAIL };

let 'n = num_elem;
let 'm = SEW;

let vm_val : bits('n) = read_vmask(num_elem, vm, zvreg);
let vs2_val : bits('n) = read_vmask(num_elem, 0b0, vs2);
let vm_val = read_vmask(num_elem, vm, zvreg);
let vs2_val = read_vmask(num_elem, 0b0, vs2);

let (_, mask) = init_masked_result_cmp(num_elem, SEW, 0, vs2_val, vm_val);

Expand Down Expand Up @@ -167,12 +158,9 @@ function clause execute(VMSBF_M(vm, vs2, vd)) = {
if illegal_normal(vd, vm) | not(assert_vstart(0)) | vd == vs2
then { handle_illegal(); return RETIRE_FAIL };

let 'n = num_elem;
let 'm = SEW;

let vm_val : bits('n) = read_vmask(num_elem, vm, zvreg);
let vs2_val : bits('n) = read_vmask(num_elem, 0b0, vs2);
let vd_val : bits('n) = read_vmask(num_elem, 0b0, vd);
let vm_val = read_vmask(num_elem, vm, zvreg);
let vs2_val = read_vmask(num_elem, 0b0, vs2);
let vd_val = read_vmask(num_elem, 0b0, vd);

let (initial_result, mask) = init_masked_result_cmp(num_elem, SEW, 0, vd_val, vm_val);
var result = initial_result;
Expand Down Expand Up @@ -208,12 +196,9 @@ function clause execute(VMSIF_M(vm, vs2, vd)) = {
if illegal_normal(vd, vm) | not(assert_vstart(0)) | vd == vs2
then { handle_illegal(); return RETIRE_FAIL };

let 'n = num_elem;
let 'm = SEW;

let vm_val : bits('n) = read_vmask(num_elem, vm, zvreg);
let vs2_val : bits('n) = read_vmask(num_elem, 0b0, vs2);
let vd_val : bits('n) = read_vmask(num_elem, 0b0, vd);
let vm_val = read_vmask(num_elem, vm, zvreg);
let vs2_val = read_vmask(num_elem, 0b0, vs2);
let vd_val = read_vmask(num_elem, 0b0, vd);

let (initial_result, mask) = init_masked_result_cmp(num_elem, SEW, 0, vd_val, vm_val);
var result = initial_result;
Expand Down Expand Up @@ -249,12 +234,9 @@ function clause execute(VMSOF_M(vm, vs2, vd)) = {
if illegal_normal(vd, vm) | not(assert_vstart(0)) | vd == vs2
then { handle_illegal(); return RETIRE_FAIL };

let 'n = num_elem;
let 'm = SEW;

let vm_val : bits('n) = read_vmask(num_elem, vm, zvreg);
let vs2_val : bits('n) = read_vmask(num_elem, 0b0, vs2);
let vd_val : bits('n) = read_vmask(num_elem, 0b0, vd);
let vm_val = read_vmask(num_elem, vm, zvreg);
let vs2_val = read_vmask(num_elem, 0b0, vs2);
let vd_val = read_vmask(num_elem, 0b0, vd);

let (initial_result, mask) = init_masked_result_cmp(num_elem, SEW, 0, vd_val, vm_val);
var result = initial_result;
Expand Down Expand Up @@ -294,12 +276,9 @@ function clause execute(VIOTA_M(vm, vs2, vd)) = {
if illegal_normal(vd, vm) | not(assert_vstart(0)) | vd == vs2
then { handle_illegal(); return RETIRE_FAIL };

let 'n = num_elem;
let 'm = SEW;

let vm_val : bits('n) = read_vmask(num_elem, vm, zvreg);
let vs2_val : bits('n) = read_vmask(num_elem, 0b0, vs2);
let vd_val : vector('n, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd);
let vm_val = read_vmask(num_elem, vm, zvreg);
let vs2_val = read_vmask(num_elem, 0b0, vs2);
let vd_val = read_vreg(num_elem, SEW, LMUL_pow, vd);

let (initial_result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val);
var result = initial_result;
Expand Down Expand Up @@ -334,11 +313,8 @@ function clause execute(VID_V(vm, vd)) = {

if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL };

let 'n = num_elem;
let 'm = SEW;

let vm_val : bits('n) = read_vmask(num_elem, vm, zvreg);
let vd_val : vector('n, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd);
let vm_val = read_vmask(num_elem, vm, zvreg);
let vd_val = read_vreg(num_elem, SEW, LMUL_pow, vd);

let (initial_result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val);
var result = initial_result;
Expand Down
33 changes: 12 additions & 21 deletions model/riscv_insts_vext_red.sail
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Expand Up @@ -26,7 +26,7 @@ mapping clause encdec = RIVVTYPE(funct6, vm, vs2, vs1, vd)
function clause execute(RIVVTYPE(funct6, vm, vs2, vs1, vd)) = {
let SEW = get_sew();
let LMUL_pow = get_lmul_pow();
let SEW_widen = SEW * 2;
let 'SEW_widen = SEW * 2;
let LMUL_pow_widen = LMUL_pow + 1;
let num_elem_vs = get_num_elem(LMUL_pow, SEW);
let num_elem_vd = get_num_elem(0, SEW_widen); /* vd regardless of LMUL setting */
Expand All @@ -35,20 +35,15 @@ function clause execute(RIVVTYPE(funct6, vm, vs2, vs1, vd)) = {

if unsigned(vl) == 0 then return RETIRE_SUCCESS; /* if vl=0, no operation is performed */

let 'n = num_elem_vs;
let 'd = num_elem_vd;
let 'm = SEW;
let 'o = SEW_widen;
let vm_val = read_vmask(num_elem_vs, vm, zvreg);
let vd_val = read_vreg(num_elem_vd, SEW_widen, 0, vd);
let vs2_val = read_vreg(num_elem_vs, SEW, LMUL_pow, vs2);
let mask = init_masked_source(num_elem_vs, LMUL_pow, vm_val);

let vm_val : bits('n) = read_vmask(num_elem_vs, vm, zvreg);
let vd_val : vector('d, bits('o)) = read_vreg(num_elem_vd, SEW_widen, 0, vd);
let vs2_val : vector('n, bits('m)) = read_vreg(num_elem_vs, SEW, LMUL_pow, vs2);
let mask : bits('n) = init_masked_source(num_elem_vs, LMUL_pow, vm_val);

var sum : bits('o) = read_single_element(SEW_widen, 0, vs1); /* vs1 regardless of LMUL setting */
var sum = read_single_element(SEW_widen, 0, vs1); /* vs1 regardless of LMUL setting */
foreach (i from 0 to (num_elem_vs - 1)) {
if mask[i] == bitone then {
let elem : bits('o) = match funct6 {
let elem : bits('SEW_widen) = match funct6 {
IVV_VWREDSUMU => to_bits(SEW_widen, unsigned(vs2_val[i])),
IVV_VWREDSUM => to_bits(SEW_widen, signed(vs2_val[i]))
};
Expand Down Expand Up @@ -99,16 +94,12 @@ function clause execute(RMVVTYPE(funct6, vm, vs2, vs1, vd)) = {

if unsigned(vl) == 0 then return RETIRE_SUCCESS; /* if vl=0, no operation is performed */

let 'n = num_elem_vs;
let 'd = num_elem_vd;
let 'm = SEW;

let vm_val : bits('n) = read_vmask(num_elem_vs, vm, zvreg);
let vd_val : vector('d, bits('m)) = read_vreg(num_elem_vd, SEW, 0, vd);
let vs2_val : vector('n, bits('m)) = read_vreg(num_elem_vs, SEW, LMUL_pow, vs2);
let mask : bits('n) = init_masked_source(num_elem_vs, LMUL_pow, vm_val);
let vm_val = read_vmask(num_elem_vs, vm, zvreg);
let vd_val = read_vreg(num_elem_vd, SEW, 0, vd);
let vs2_val = read_vreg(num_elem_vs, SEW, LMUL_pow, vs2);
let mask = init_masked_source(num_elem_vs, LMUL_pow, vm_val);

var sum : bits('m) = read_single_element(SEW, 0, vs1); /* vs1 regardless of LMUL setting */
var sum = read_single_element(SEW, 0, vs1); /* vs1 regardless of LMUL setting */
foreach (i from 0 to (num_elem_vs - 1)) {
if mask[i] == bitone then {
sum = match funct6 {
Expand Down
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