Handle address translation for misaligned loads and stores better #861

pmundkur · 2025-04-15T20:03:18Z

Refactor the LOAD and STORE instruction so they split misaligned
accesses into multiple sub-accesses and perform address translation
separately. This means we should handle the case where a misaligned
access straddles a page boundary in a sensible way, even if we don't
yet cover the full range of possibilities allowed for any RISC-V
implementation.

There are options for the order in which misaligned happen, i.e. from
high-to-low or from low-to-high as well as the granularity of the splitting,
either all the way to bytes or to the largest aligned size. The splitting
can also be disabled if an implementation supports misaligned accesses in hardware.

In addition tidy up the implementation in a few ways:

Very long lines on the LOAD encdec were fixed by adding a helper
Add some linebreaks in the code so it reads as less claustrophobic
Ensure we use the same names for arguments in encdec/execute/assembly.
Previously we used 'size' and 'width'. I opted for 'width' consistently.

Co-authored-by: Alasdair Armstrong [email protected]

github-actions · 2025-04-15T20:15:46Z

Test Results

400 tests ±0 400 ✅ ±0 1m 44s ⏱️ -1s
1 suites ±0 0 💤 ±0
1 files ±0 0 ❌ ±0

Results for commit f25e661. ± Comparison against base commit 3bdcf27.

♻️ This comment has been updated with latest results.

nadime15

Looks awesome! Just a few comments

nadime15 · 2025-04-16T16:58:46Z

model/riscv_insts_base.sail

+      match vmem_write(vaddr, width_bytes, data, aq, rl, false) {
+        Ok(_) => RETIRE_SUCCESS,
+        Err(vaddr, e) => {
+          handle_mem_exception(vaddr, e);
+          return RETIRE_FAIL
        }


Suggested change

match vmem_write(vaddr, width_bytes, data, aq, rl, false) {

Ok(_) => RETIRE_SUCCESS,

Err(vaddr, e) => {

handle_mem_exception(vaddr, e);

return RETIRE_FAIL

}

match vmem_write(vaddr, width_bytes, data, aq, rl, false) {

Ok(_) => RETIRE_SUCCESS,

Err(vaddr, e) => { handle_mem_exception(vaddr, e); return RETIRE_FAIL }

To match model/riscv_insts_fext.sail and the rest.

This will change anyway once I rebase on top of #755.

nadime15 · 2025-04-16T16:59:20Z

model/riscv_insts_fext.sail

+        Err(vaddr, e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL },
+        Ok(result)    => { F(rd) = nan_box(result); RETIRE_SUCCESS }


Suggested change

Err(vaddr, e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL },

Ok(result) => { F(rd) = nan_box(result); RETIRE_SUCCESS }

Ok(result) => { F(rd) = nan_box(result); RETIRE_SUCCESS }

Err(vaddr, e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL },

Thanks, done.

model/riscv_vmem_utils.sail

nadime15 · 2025-04-16T17:35:54Z

model/riscv_vmem_utils.sail

+function prop_access_within_is_aligned(addr : bits(32), bytes : bits(4)) -> bool = {
+  let bytes = unsigned(zero_extend(32, 0b1) << unsigned(bytes));
+  if bytes > 0 then {
+    access_within(addr, bytes, bytes) == (fmod_int(unsigned(addr), bytes) == 0)


What is fmod_int() doing?

Good question. It's integer modulus. I now notice there are two of these: emod_int and fmod_int. The first always returns a positive value, the second ('f' stands for 'floor' according to GMP docs) retains the sign of the divisor. Not sure the difference matters here. @Alasdair?

fdiv and fmod are flooring, so they round down always. tdiv and tmod are truncating so they round towards zero. emod and ediv are euclidian division. Wikipedia has good summary of the differences here https://en.wikipedia.org/wiki/Modulo#Variants_of_the_definition

The only reason we really have euclidian division is it's the definition used in the SMT integer theory

Seems like since these are both positive, they’d all be the same? In which case we might as well use %, which is already defined in the prelude to mean emod.

The SMT properties check out in both cases, so I'll switch it to % when I rebase.

pmundkur · 2025-04-18T19:53:37Z

The last push rebased on master and refactored #467 to pull the ext_data_get_addr calls into the vmem_utils helpers. This cleans up the calling code significantly, and (hopefully) isolates almost all the RVWMO-relevant pieces for usual loads/stores into vmem_utils.

As before, AMOs, fetch, and CBOs are untouched.

There is a slight difference in alignment checks for LOADRES/STORECON in the read/write helpers. I'll try to clean it up before final merge.

@Alasdair could you check if this breaks RVWMO modelling in any way? There's a comment in vmem_utils that I retained from your #467 that may need adjusting?

pmundkur · 2025-04-18T20:08:36Z

Hmm, the CI failure is odd. It's building locally (and passing tests) with Sail 0.19.

pmundkur · 2025-04-18T20:18:52Z

Hmm, the CI failure is odd. It's building locally (and passing tests) with Sail 0.19.

Drat, I think this is triggering a bug in the smt backend of Sail, both 0.19 and the latest master.

pmundkur · 2025-04-22T00:22:58Z

@bacam Could you take a look at this Rocq failure? Perhaps it's being triggered by the match being inside a repeat? Adding a let _ : unit = match { ... }; annotation did not help.

jordancarlin

Overall looking like an amazing simplification!

Makefile.old

model/riscv_vmem_utils.sail

jordancarlin · 2025-04-21T03:40:51Z

model/riscv_vmem_utils.sail

+
+  // If the Zama16b extension is enabled, the region_width must be at least 16
+  let region_width = if currentlyEnabled(Ext_Zama16b) then {
+    max_int(16, region_width)


Suggested change

max_int(16, region_width)

max(16, region_width)

model/riscv_vmem_utils.sail

jordancarlin · 2025-04-22T05:58:33Z

doc/ReadingGuide.md

+  See the [Virtual Memory Notes](./notes_Virtual_Memory.adoc) for
+  details.
+
+- The `riscv_vmem_utils.sail` file provides a higher level interface


Might be worth adding a more detailed description to the notes_Virtual_Memory.adoc file.

I'm not sure what can go in there in addition to what's already described in comments in riscv_vmem_utils.sail.

model/riscv_vmem_utils.sail

bacam · 2025-04-25T17:09:24Z

model/riscv_vmem_utils.sail

+  /* If the load is misaligned or an allowed misaligned access, split into `n`
+     (single-copy-atomic) memory operations, each of `bytes` width. If the load is
+     aligned, then `n` = 1 and bytes will remain unchanged. */
+  let ('n, bytes) = split_misaligned(vaddr, width);


We can work around the Rocq problem by changing bytes to 'bytes - this gives data a printable type that can be used in rewrites. (Rocq also needs a couple of termination measures, but I'll give those separately.)

bacam · 2025-04-25T17:11:00Z

For Rocq output we also need to add two termination measures to riscv_termination.sail:

termination_measure vmem_write_addr repeat n
termination_measure vmem_read repeat n

Although it would be helpful if someone could check that n is the correct limit in both cases.

pmundkur · 2025-04-25T17:55:22Z

For Rocq output we also need to add two termination measures to riscv_termination.sail:
termination_measure vmem_write_addr repeat n
termination_measure vmem_read repeat n
Although it would be helpful if someone could check that n is the correct limit in both cases.

Yeah, I think n is the correct limit since the loop should repeat at most n times in both cases.

Your suggestions fixed the build. Thanks!

model/riscv_vmem_utils.sail

nadime15

Looks good!

It would be great to prioritize and get this merged so work on the other PRs can move forward!

jordancarlin

LGTM now that the configuration issue has been resolved. This will be great to get in!

pmundkur · 2025-05-05T14:26:14Z

I'll merge this tomorrow.

Timmmm

Do you mind waiting a day for me to take a more detailed look? Sorry I've been putting it off but I'll look tomorrow. I'd like to make sure it works for us and also with #866.

Also I think we really need to clean up the AccessType system because the behaviour is kind of half split between AccessType and the res/aq/con flags. I kind of think we should remove those flags and move everything into AccessType. (In future of course.)

model/riscv_insts_aext.sail

model/riscv_vmem_utils.sail

config/default.json

Refactor the LOAD and STORE instruction so they split misaligned accesses into multiple sub-accesses and perform address translation separately. This means we should handle the case where a misaligned access straddles a page boundary in a sensible way, even if we don't yet cover the full range of possibilities allowed for any RISC-V implementation. There are options for the order in which misaligned happen, i.e. from high-to-low or from low-to-high as well as the granularity of the splitting, either all the way to bytes or to the largest aligned size. The splitting can also be disabled if an implementation supports misaligned accesses in hardware. In addition tidy up the implementation in a few ways: - Very long lines on the LOAD encdec were fixed by adding a helper - Add some linebreaks in the code so it reads as less claustrophobic - Ensure we use the same names for arguments in encdec/execute/assembly. Previously we used 'size' and 'width'. I opted for 'width' consistently. Primary author: Alasdair Armstrong <[email protected]> Co-authored-by: Alasdair Armstrong <[email protected]>

Add some comments on the API available from `vmem_utils`. Update Makefile.old for SMT properties. Update the ReadingGuide.

Timmmm

Thanks, LGTM!

I think we will probably want to make this more configurable in future, but it at least fixes the page straddling problem which is currently totally broken... 🚀

Lean does not use termination measures for loops, so we need to guard their definitions. The problematic measures was introduced by #861.

pmundkur requested a review from Alasdair April 15, 2025 20:04

nadime15 reviewed Apr 16, 2025

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Configuration validation #860

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Use result type for TR_Result instead of union #875

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Test Lean/Coq output when it's all working #744

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Unprintable types cause type-checking problems during rewrites rems-project/sail#1261

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Generating SMT files #903

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pmundkur and others added 2 commits May 6, 2025 09:43

Update the F/D and vector loads/stores to use the vmem_utils helpers.

3477a6f

Add some comments on the API available from `vmem_utils`. Update Makefile.old for SMT properties. Update the ReadingGuide.

pmundkur force-pushed the ldst_misaligned_take2 branch from 8b7febc to 3477a6f Compare May 6, 2025 14:49

Add an access-type parameter to the vmem_{read,write} functions.

f25e661

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Timmmm changed the title ~~Better handling of misaligned accesses (take 2)~~ Better handling of misaligned accesses May 7, 2025

Timmmm changed the title ~~Better handling of misaligned accesses~~ Handle address translation for misaligned loads and stores better May 7, 2025

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Merged via the queue into riscv:master with commit cd50ea2 May 7, 2025
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ineol mentioned this pull request May 7, 2025

Lean: fix termination measures #924

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This was referenced May 7, 2025

Handle address translation for misaligned loads and stores better #467

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misaligned load/store on page crossing doesn't tablewalk for second page #49

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Big endianness Support added #751

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github-merge-queue bot pushed a commit that referenced this pull request May 8, 2025

Lean: fix termination measures (#924)

2e2e8e0

Lean does not use termination measures for loops, so we need to guard their definitions. The problematic measures was introduced by #861.

jordancarlin mentioned this pull request May 12, 2025

Add support for Zcmp extension #730

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pmundkur mentioned this pull request May 22, 2025

Add support for Pointer Masking Extension (Zpm) #969

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pmundkur deleted the ldst_misaligned_take2 branch June 10, 2025 15:33

		Err(vaddr, e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL },
		Ok(result) => { F(rd) = nan_box(result); RETIRE_SUCCESS }

Handle address translation for misaligned loads and stores better #861

Handle address translation for misaligned loads and stores better #861

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