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Change XLEN and FLEN to be configure-time options #870

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Merged
merged 1 commit into from
Jun 27, 2025

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Timmmm
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@Timmmm Timmmm commented Apr 17, 2025

This means you only need to compile the emulator once in order to support RV32F, RV32D, RV64F and RV64D. The emulator binary has been renamed to sail_riscv_sim.

XLEN is controlled by the base.xlen config value. FLEN is controlled by extensions.{F,D}.supported.

Some backends (Lean etc.) still need a compile-time config so for those we still support building multiple configs.

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This is awesome! It looks like the upstream issues are fixed. Are there any other issues preventing this coming out of draft?

@Timmmm Timmmm force-pushed the user/timh/xlen_flen branch from 11d975a to 336ba9f Compare April 22, 2025 10:59
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Timmmm commented Apr 22, 2025

This is awesome! It looks like the upstream issues are fixed. Are there any other issues preventing this coming out of draft?

Getting closer but I hit another issue: rems-project/sail#1251

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Timmmm commented Apr 22, 2025

Also I need to:

  1. Re-enable/fix the tests.
  2. Remove flen or F/D as @jordancarlin suggested.
  3. Maybe make the config option be xlen instead of log2_xlen_bytes which is not very intutive! Since there are only 2 options I think we can just go backwards like: type xlen_bytes : Int = if xlen == 32 then 4 else 8. Hopefully that will work.
  4. Update the readme.
  5. Ideally benchmark the performance hit. I suspect it will be relatively minor but it might not be.

And we'll need to wait for a new Sail compiler release after it's working.

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Timmmm commented Apr 22, 2025

Ok I got the RV64 first party test passing! Still need to do all the todos I mentioned.

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Timmmm commented Apr 23, 2025

I did have a crazy idea - what if we just take the xlen setting from the ELF file? :-D

On balance, probably a bad idea. Explicitness is good. Just thought I'd mention it!

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I did have a crazy idea - what if we just take the xlen setting from the ELF file? :-D

On balance, probably a bad idea. Explicitness is good. Just thought I'd mention it!

Something to think about down the road maybe. I think we can technically even find out which extensions an elf was compiled with if we really wanted to. Might be nice to be able to just run an elf without thinking about the config.

For verification purposes though (which I think is one of the primary uses of the Sail model), you want the model to exactly match an implementation no matter what the elf file being passed in is. Maybe there could be two different modes in the future: use the values from a config file if one is given and parse the elf if not.

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Timmmm commented Apr 23, 2025

This basically works now. All the tests pass. Remaining todos:

  1. Benchmark.
  2. Come up with a better system for the config files than copy/pasting them. Though tbh if we only have 2/3 files that's maybe the best way anyway.
  3. Ideally get rid of the weird _rv suffix on riscv_sim_rv, but I think that might be best deferred until we merge the RVFI version so there's only a single emulator.
  4. Wait for new Sail compiler release.

@Timmmm Timmmm force-pushed the user/timh/xlen_flen branch from e3e76fa to 551e8f8 Compare April 28, 2025 15:36
@jordancarlin jordancarlin added the tgmm-agenda Tagged for the next Golden Model meeting agenda. label May 12, 2025
@Timmmm Timmmm added the pending sail compiler PRs/issues that can only be resolved with a newer release of the Sail compiler label May 19, 2025
@Timmmm Timmmm mentioned this pull request May 19, 2025
@Timmmm Timmmm force-pushed the user/timh/xlen_flen branch from 551e8f8 to 97142a0 Compare May 19, 2025 09:13
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Timmmm commented May 19, 2025

This also needs changes to the types of the callback interface now (fbits -> sbits). I'll do it at some point.

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@Timmmm I updated the types for the callbacks to get this building again and then removed ${arch} from the c simulator. As discussed during the meeting, I've renamed the simulator sail_riscv_sim.

I also realized that we need to maintain separate targets for the theorem provers since they take a compile time config file, so I added those back in.

@jordancarlin jordancarlin force-pushed the user/timh/xlen_flen branch from 52c51d2 to 5dd40e2 Compare May 20, 2025 09:13
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Not sure why the SMT target is failing to populate the config values from the config file, but other than that, this seems to be working now (barring the new Sail release).

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Thanks! LGTM - just a few minor nits.

@jordancarlin jordancarlin force-pushed the user/timh/xlen_flen branch 2 times, most recently from 293ebf5 to b85125c Compare May 21, 2025 20:05
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Other than waiting on the new sail release, I still need to sort out why all of the theorem provers (including the SMT target) are giving the following error:

Error:
riscv_vmem_utils.sail:47.63-106:
47 |function sys_misaligned_allowed_within_exp() -> range(0, 11) = config memory.misaligned.allowed_within_exp
   |                                                               ^-----------------------------------------^
   | SMT solver returned unexpected status 1

@Alasdair @Timmmm any ideas?

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github-actions bot commented Jun 14, 2025

Test Results

400 tests  ±0   400 ✅ ±0   1m 28s ⏱️ +3s
  1 suites ±0     0 💤 ±0 
  1 files   ±0     0 ❌ ±0 

Results for commit 7b8122f. ± Comparison against base commit f4a94a3.

♻️ This comment has been updated with latest results.

@jordancarlin jordancarlin removed the pending sail compiler PRs/issues that can only be resolved with a newer release of the Sail compiler label Jun 15, 2025
@Timmmm Timmmm force-pushed the user/timh/xlen_flen branch from aac864e to 3626360 Compare June 16, 2025 10:45
@Timmmm Timmmm marked this pull request as ready for review June 16, 2025 13:37
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I might be being dumb but this is giving the following error when building the SMT target:

Error:
riscv_device_tree.sail:190.25-56:
190 |  let clock_freq : int = config platform.clock_frequency;
    |                         ^-----------------------------^
    | Runtime configuration is not supported when generating code for target 'smt'
    | An explicit configuration should be provided with the --config option.

Reasonable, except it does use the --config option:

cd /home/me/workspace/sail-riscv/model && /home/me/workspace/sail-riscv/build/sail/bin/sail --smt -o /home/me/workspace/sail-riscv/build/model/model --require-version 0.19.1 --config /home/me/workspace/sail-riscv/config/rv32d.json prelude.sail ... lots of sail files ... main.sail

It happens when one of the config options is missing from the json file. Looks like part of one of my patches was also lost during the rebase. Pushed an updated version that should resolve these issues.

Come up with a better system for the config files than copy/pasting them. Maybe. Tbh I'm ok with copy/paste to start with.

Not sure that there is a better option than copy/pasting because there are various extensions that should be different between RV32/RV64. For example, Zcf should be on in RV32 but not RV64. Similar for the Sv* extensions.

These should be quite easy to handle with a simple CMake substition:

"Zcf" : { supported: @CONFIG_IS_RV32@ }
"Sv32" : { supported: @CONFIG_IS_RV32@ } (or True if it works for RV64).
"Sv48" : { supported: @CONFIG_IS_RV64@ }
and then just call configure_file() with those variables set appropriately.

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Timmmm commented Jun 20, 2025

I'm still slightly partial to just copy & pasting. It's only two files and I think it's unlikely to grow... and I think there's a lot of value in having the file in the source tree that people can easily copy & paste and modify without having to dig it out from the build directory.

Would you be ok with merging this as-is and using configure_file() later if it becomes a problem (e.g. if they get out of sync)?

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Timmmm commented Jun 20, 2025

I do think we could delete default.json and just use the rv64d one as the default though. There's no need for three files...

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I do think we could delete default.json and just use the rv64d one as the default though. There's no need for three files...

Yes if there are only two files I'd be happy with this.

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Timmmm commented Jun 25, 2025

Ok I think this is ready to go. I finally got around to benchmarking it. First 3 million instructions of booting Linux (this is not very many - it actually doesn't get through OpenSBI). With a recent sail2 commit:

  • master: 53 kIPS
  • This PR: 48 kIPS

Considering with the 0.19.1 compiler it's like 9 kIPS and nobody noticed, I think that's fine. It would be nice to work back up to ~500 kIPS which is what Sail was capable of a while ago, but we'll have to do some work for that. I have some ideas.

@Timmmm Timmmm force-pushed the user/timh/xlen_flen branch from fa1531d to 52f8c43 Compare June 25, 2025 13:42
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This is awesome! We should merge this soon to avoid more painful rebasing.

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This is great!

@jordancarlin jordancarlin force-pushed the user/timh/xlen_flen branch from 52f8c43 to b72811b Compare June 27, 2025 06:41
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Rebased again. Would definitely be nice to get merged soon since just about any change to the CMake or config files forces this be rebased.

@jordancarlin jordancarlin force-pushed the user/timh/xlen_flen branch from b72811b to a148093 Compare June 27, 2025 06:53
This means you only need to compile the emulator once in order to support RV32F, RV32D, RV64F and RV64D.

Co-authored-by: Jordan Carlin <[email protected]>

Remove `default.json` and use RV64D by default directly
@Timmmm Timmmm force-pushed the user/timh/xlen_flen branch from a148093 to 7b8122f Compare June 27, 2025 08:26
@Timmmm Timmmm added the will be merged Scheduled to be merged in a few days if nobody objects label Jun 27, 2025
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Timmmm commented Jun 27, 2025

Didn't notice your rebase so I also rebased, and we both made slightly different rebase mistakes which I have fixed. :-D

I will merge this today if nobody objects!

@Timmmm Timmmm added this pull request to the merge queue Jun 27, 2025
@Timmmm Timmmm removed this pull request from the merge queue due to a manual request Jun 27, 2025
@Timmmm Timmmm added this pull request to the merge queue Jun 27, 2025
Merged via the queue into riscv:master with commit e1fedba Jun 27, 2025
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@Timmmm Timmmm deleted the user/timh/xlen_flen branch July 2, 2025 07:56
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